HDMI Intel® FPGA IP User Guide

ID 683798
Date 4/22/2022
Public

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Document Table of Contents

9.4.1. HDMI Sink CV2AXI Register Summary

Table 147.  HDMI Sink CV2AXI Register Summary
Base Address 0x100
Address Register Description
0x50 STATUS CV2AXI status register

Refer to Table: STATUS (0x50).

0x51 RESERVED Reserved
0x52 ACTIVE_SAMPLE_COUNT CV2AXI active sample count

Refer tp Table: ACTIVE SAMPLE COUNT (0x52).

0x53 F0_ACTIVE_LINE_COUNT CV2AXI F0 active line count

Refer to Table: F0_ACTIVE_LINE_COUNT (0x53).

0x54 F1_ACTIVE_LINE_COUNT CV2AXI F1 active line count.

Refer to Table: F1_ACTIVE_LINE_COUNT (0x54).

0x55 TOTAL_SAMPLE_COUNT CV2AXI total sample count.

Refer to Table: TOTAL_SAMPLE_COUNT (0x55).

0x56 F0_TOTAL_LINE_COUNT CV2AXI F0 total line count.

Refer to Table: F0_TOTAL_LINE_COUNT (0x56).

0x57 F1_TOTAL_LINE_COUNT CV2AXI F1 total line count.

Refer to Table: F1_TOTAL_LINE_COUNT (0x57)

0x58 - 0x5B RESERVED Reserved
0x5C COLOR_PATTERN CV2AXI color pattern.

Refer to Table: COLOR_PATTERN (0x5C).

0x5D – 0x63 RESERVED Reserved
0x64 CONTROL CV2AXI control register.

Refer to Table: Control (0x64)

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