HDMI Intel® FPGA IP User Guide

ID 683798
Date 4/22/2022
Public

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4.3.1.6. DCFIFO

The DCFIFO transfers data from the RX transceiver recovered clock domain to the RX link speed clock domain. The DCFIFO transfers data from the TX link speed clock domain to the TX transceiver parallel clock out domain.
  • Sink
    • When the Multirate Reconfig Controller (RX) detects an incoming input stream that is below the transceiver minimum link rate, the DCFIFO accepts the data from the Oversampler with data valid pulse as write request asserted every 5 clock cycles.
    • Otherwise, it accepts data directly from the transceiver with write request asserted at all times.
  • Source
    • When Nios II processor determines the outgoing data stream is below the TX transceiver minimum link rate, the TX transceiver accepts the data from the Oversampler (TX).
    • Otherwise, the TX transceiver reads data directly from the DCFIFO with read request asserted at all times.

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