HDMI Intel® FPGA IP User Guide

ID 683798
Date 4/22/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.1.13. Sink FRL Descrambler and Decoder

FRL data is decoded using 16B/18B decoder. The HDMI RX core then descrambles the decoded data to obtain the FRL super block.