HDMI Intel® FPGA IP User Guide

ID 683798
Date 4/22/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.1.20. Avalon Memory-Mapped Demultiplexer

Avalon® memory-mapped demultiplexer demultiplexes a single Avalon slave interface to four Avalon master for I2C Master, HDMI register, AXI4-stream to clocked video converter, and HDCP (for future use) based on the respective address offset. The slave on the Avalon memory-mapped demultiplexer is operating at word addressing.
Master Address Offset Size


HDMI I2C Master 0x0000 16 For HDMI DDC channel for accessing external sink SCDC and EDID and for link training function
AXI4-stream to clocked video converter 0x0010 512 Control and status register on AXI4-stream to clocked video converter
HDCP register 0x0210 256 Reserved for HDCP registers
HDMI register 0x0310 256 Control and status register on HDMI core