HDMI Intel® FPGA IP User Guide

ID 683798
Date 4/22/2022
Public

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9.1.1.5. AVI_CONTROL (0x08)

Table 69.  AVI_CONTROL (0x08)
Name Bit(s) Access Description Reset
reserved 31:1 - - -
AVI disable 0 RW When set to 1, HDMI TX core does not send AVI infoframes from the AVI_PACKET_DATA registers When set to 0, HDMI TX core sends AVI infoframes from the AVI_PACKET_DATA registers 0x0

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