HDMI Intel® FPGA IP User Guide

ID 683798
Date 4/22/2022

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6.1.23. RX AXI4-Stream Auxiliary Bridge

The AXI4-Stream auxiliary interface is a 32-bit wide bus which carries HDMI sideband data such as infoframe or audio packets. It can be used for passthrough purposes when forwarding video from receiver to a transmitter or when used in conjunction with a DMA engine, as a method of saving HDMI packet data to memory with the minimum of CPU overhead.

The packet header is received first, followed by subpacket 0, subpacket 1, subpacket 2 and subpacket 3. Subpacket 0 contains packet bytes 0 to 6 (PB0-PB6), subpacket 1 contains packet byte 7 to 13 (PB7-PB13), subpacket 2 contains packet byte 14 to 20 (PB14-PB20) and subpacket 4 contains packet byte 21 to 27 (PB21-PB27). Refer to HDMI Specification 1.4b Section Data Island Packet Construction for more details on the subpacket. Since each subpacket contains 64 bits, each subpacket is carried by two AXI4-stream auxiliary data of 32-bit wide.

An example transfer sequence for a single complete data packet is shown in the figure below. Transfers conform to the AXI4-stream standard.

The transfer request is initiated by axi4s_aux_in_tvalid going high. The final beat of the transfer is indicated by axi4s_aux_in_tlast going high. All transfers must be exactly nine beats long. The axi4s_aux_in_data needs to be hold when axi4s_aux_in_tready is low.

RX AXI4-stream auxiliary bridge converts auxiliary data from Avalon streaming format to AXI4 streaming format. RX AXI4-stream auxiliary bridge also contains a DCFIFO for clock domain crossing from vid_clk to mgmt_clk.