HDMI Intel® FPGA IP User Guide

ID 683798
Date 4/22/2022
Public

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7.1. HDMI Source Parameters

Table 62.  HDMI Source Parameters
Parameter Value Description
Device family
  • Intel® Agilex™ F-tile
  • Intel® Stratix® 10
  • Intel® Arria® 10
  • Intel® Cyclone® 10 GX
  • Arria V

  • Stratix V

Targeted device family. This parameter inherits the value from the project device.
Direction

Transmitter

Receiver

Select HDMI transmitter.
Pixels per clock 2 or 8 pixels per clock

Determines how many pixels are processed per clock.

  • When you turn off Support FRL, supports 2 pixels per clock.
  • When you turn on Support FRL, supports 8 pixels per clock.
Note: This parameter is available only with Intel® Arria® 10 and Intel® Stratix® 10 devices.
Transceiver width 20 or 40 bits Determines the required transceiver width. The transceiver width depends on the number of TMDS symbols processed in parallel (symbols per clock).
  • When you turn off Support FRL, transceiver width is 20 bits (2 symbols per clock).
  • When you turn on Support FRL, transceiver width is 40 bits (4 symbols per clock).
Note: This parameter is available only with Intel® Arria® 10 and Intel® Stratix® 10 devices.
Enable active video protocol AXIS-VVP Full,None Determines the input video data format.

When set to AXIS-VVP full, the video input follows the AXI streaming VVP full specification (Intel FPGA Streaming Video Protocol Specification).

When set to None, the video input is in clocked video format.

Support auxiliary On, Off Determines if auxiliary channel encoding is included. This parameter is turned on by default.

This parameter is always turned on when Support FRL is enabled.

Support deep color On, Off

Determines if the core can encode deep color formats. This parameter is turned on by default.

Support audio On, Off

Determines if the core can encode audio data.

To enable this parameter, you must also enable the Support auxiliary parameter. This parameter is turned on by default.

Support FRL On, Off

Turn on to enable the FRL path.

When enabled, the clock domains for the auxiliary and audio ports, and the internal modules are different Refer to the block diagram for more details.

Note: This parameter is available only with Intel® Arria® 10 and Intel® Stratix® 10 devices.
Support HDCP 2.3 On, Off

Turn on to enable HDCP 2.3 TX support. This parameter can only be used with Intel® Arria® 10 and Intel® Stratix® 10 devices.

Note: The HDCP-related parameters are not included in the Intel® Quartus® Prime Pro Edition software. To access the HDCP feature, contact Intel at https://www.intel.com/content/www/us/en/broadcast/products/programmable/applications/connectivity-solutions.html.
Support HDCP 1.4 On, Off

Turn on to enable HDCP 1.4 TX support. This parameter can only be used with Intel® Arria® 10 and Intel® Stratix® 10 devices.

Note: The HDCP-related parameters are not included in the Intel® Quartus® Prime Pro Edition software. To access the HDCP feature, contact Intel at https://www.intel.com/content/www/us/en/broadcast/products/programmable/applications/connectivity-solutions.html.
Support HDCP Key Management On, Off Turn on to enable HDCP key management support. You can only turn on this parameter if you turn on the Support HDCP 1.4 or Support HDCP 2.3 parameters.
Note:
  1. The HDCP-related parameters are not included in the Intel® Quartus® Prime Intel® Quartus® Prime Pro EditionIntel Quartus Prime Pro Edition software. To access the HDCP feature, contact Intel at https://www.intel.com/content/www/us/en/broadcast/products/programmable/applications/connectivity-solutions.html.
  2. The HDCP key management support from version 21.3 onwards is not compatible with the KEYENC version 21.2 and earlier. You need to re-encrypt the HDCP production keys using the KEYENC version 21.3 onwards. Refer to HDMI Intel Arria 10 FPGA IP Design Example User Guide and HDMI Intel Stratix 10 FPGA IP Design Example User Guide for more details.
Include I2C Master/Slave On, Off

Turn on to include a pair of I2C master on TX for DDC operation.

When Enable Active Video Protocol is set to AXIS-VVP Full, Advanced Configuration tab appears in the HDMI source GUI. Advanced Configuration tab contains the parameter below.

Parameter Value Description
Video in and out use the same clock On, Off
  • When set to On, the AXI2CV core input and output are driven by the same clock source. You shall drive vid_clk and axi4s_clk with the same fixed clock source.
  • When set to Off, you shall drive vid_clk with the actual pixel rate / pixels per clock.

You shall set the axi4s_clk to a fixed clock frequency. The axi4s_clk clock frequency must be equal or greater than the actual pixel rate / pixels per clock.

Enable user-defined packet support On, Off When set to On, user defined packet support is enabled. You can transmit auxiliary data through the user packet register configuration using host processor. When set to Off, user defined packet support is disabled.
Enable AXIS auxiliary packet interface On, Off When set to On, AXI4-stream auxiliary packet interface is enabled. You can transmit auxiliary data through AXI4-stream auxiliary packet interface. When set to Off, AXI4-stream auxiliary packet interface support is disabled.

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