HDMI Intel® FPGA IP User Guide

ID 683798
Date 4/22/2022
Public

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Document Table of Contents

9.1.1. HDMI Source Core Register Summary

Table 64.  HDMI Source Core Register Summary
Base Address 0x310
Address Register Description
0x00 STATUS_CONTROL (0x00) HDMI TX status and control register. Indicates hotplug detect on the HDMI TX. You can also set TMDS ratio, AVMUTE set and AVMUTE clear bit, DVI or HDMI mode and scrambler enable in this register.

Refer to Table: STATUS_CONTROL (0x00).

0x01 IRQ_STATUS HDMI TX interrupt status for the hotplug detect and video overflow.

Refer to Table: IRQ_STATUS (0x01).

0x02 IRQ_MASK HDMI TX interrupt mask for the interrupt status bit.

Refer to Table: IRQ_MASK (0x02).

0x03 VIDEO_FORMAT HDMI TX video format register. Use this register to set the oversample factor and colour depth.

Refer to Table: VIDEO_FORMAT (0x03).

0x08 AVI_CONTROL HDMI TX AVI control register to enable or disable AVI infoframe transmission through AVI infoframe register.

Refer to Table: AVI_CONTROL (0x08).

0x09 AVI_PACKET_DATA0 HDMI TX AVI packet bye 0-3.

Refer to Table: AVI_PACKET_DATA0 (0x09).

0x0A AVI_PACKET_DATA1 HDMI TX AVI packet bye 4-7.

Refer to Table: AVI_PACKET_DATA0 (0x0A).

0x0B AVI_PACKET_DATA2 HDMI TX AVI packet bye 8-11.

Refer to Table: AVI_PACKET_DATA2 (0x0B).

0x0C AVI_PACKET_DATA3 HDMI TX AVI packet bye 12-14.

Refer to AVI_PACKET_DATA3 (0x0C).

0x0D VSI_CONTROL HDMI TX VSI control register to enable or disable VSI infoframe transmission through VSI infoframe register.

Refer to Table: AVI_PACKET_DATA3 (0x0C).

0x0E VSI_PACKET_HEADER HDMI TX VSI packet header.

Refer to Table: VSI_PACKET_HEADER (0x0E).

0x0F VSI_PACKET_DATA0 HDMI TX VSI packet byte 0-3.

Refer to VSI_PACKET_DATA0 (0x0F).

0x10 VSI_PACKET_DATA01 HDMI TX VSI packet byte 4-6.

Refer to Table: VSI_PACKET_DATA (0x10).

0x12 USER_PACKET_STATUS_CONTROL HDMI TX user packet control register. Use this register to set the user packet mode and the slot number to write the packet data. This register also indicates the user packet interface is busy and the number of available user packet slots.

Refer to Table: USER_PACKET_STATUS_CONTROL (0x12)

0x13 USER_PACKET_HEADER HDMI TX user packet header byte 0-2.

Refer to Table: USER_PACKET_HEADER (0x013).

0x14 USER_PACKET_DATA0 HDMI TX user packet data byte 0-3.

Refer to Table: USER_PACKET_DATA0 (0x014).

0x15 USER_PACKET_DATA1 HDMI TX user packet data byte 4-6

Refer to Table: USER_PACKET_DATA1 (0x015).

0x16 USER_PACKET_DATA2 HDMI TX user packet data byte 7-10.

Refer to Table: USER_PACKET_DATA2 (0x016).

0x17 USER_PACKET_DATA3 HDMI TX user packet data byte 11-13.

Refer to USER_PACKET_DATA3 (0x017).

0x18 USER_PACKET_DATA4 HDMI TX user packet data byte 14-17.

Refer to Table: USER_PACKET_DATA4 (0x018).

0x19 USER_PACKET_DATA5 HDMI TX user packet data byte 18-20.

Refer to Table: USER_PACKET_DATA5 (0x019).

0x1A USER_PACKET_DATA6 HDMI TX user packet data byte 21-24.

Refer to Table: USER_PACKET_DATA6 (0x01A).

0x1B USER_PACKET_DATA7 HDMI TX user packet data byte 25-27.

Refer to Table: USER_PACKET_DATA7 (0x01B).

0x20 AUDIO_INFOFRAME_CONTROL HDMI TX audio inforframe control to enable or disable audio infoframe transmission through audio infoframe register.

Refer to Table: AUDIO_INFOFRAME_CONTROL (0x20).

0x21 AUDIO_INFOFRAME _PACKET_DATA0 HDMI TX audio inforframe packet data 0.

Refer to Table: AUDIO_INFOFRAME_PACKET_DATA0 (0x21).

0x22 AUDIO_INFOFRAME _PACKET_DATA1 HDMI TX audio inforfframe packet data 1.

Refer to Table: AUDIO_INFOFRAME_PACKET_DATA1 (0x22).

0x24 AUDIO_METADATA_CONTROL HDMI TX audio metadata control to enable or disable audio metadata transmission through audio metadata register.

Refer to AUDIO_METADATA_CONTROL (0x24).

0x25 AUDIO_METADATA_PACKET_HEADER HDMI TX audio metadata packet header byte 0-2.

Refer to Table: AUDIO_METADATA_PACKET_HEADER (0x025).

0x26 AUDIO_METADATA_PACKET_DATA0 HDMI TX audio metadata packet data byte 0-3.

Refer to Table: AUDIO_METADATA_PACKET_DATA0 (0x026).

0x27 AUDIO_METADATA_PACKET_DATA1 HDMI TX audio metadata packet data byte 4-6.

Refer to Table: AUDIO_METADATA_PACKET_DATA1 (0x027).

0x28 AUDIO_METADATA_PACKET_DATA2 HDMI TX audio metadata packet data byte 7-10.

Refer to Table: AUDIO_METADATA_PACKET_DATA2 (0x028)

0x29 AUDIO_METADATA_PACKET_DATA3 HDMI TX audio metadata packet data byte 11-13. Refer to Table: AUDIO_METADATA_PACKET_DATA3 (0x029).
0x2A AUDIO_METADATA_PACKET_DATA4 HDMI TX audio metadata packet data byte 14-17.

Refer to Table: AUDIO_METADATA_PACKET_DATA4 (0x02A).

0x2B AUDIO_METADATA_PACKET_DATA5 HDMI TX audio metadata packet data byte 18-19.

Refer to Table: AUDIO_METADATA_PACKET_DATA5 (0x02B).

0x31 SCDC_FRL_CONTROL HDMI TX SCDC FRL control register. Use this register to set the FRL link training pattern, FRL rate, and FRL start flag.

Refer to Table: SCDC_FRL_CONTROL (0x031).

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