HDMI Intel® FPGA IP User Guide

ID 683798
Date 4/22/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

9.2.2.18. VIDEO_MODE_F0_VERTICAL_RISING (0x62)

Table 117.  VIDEO_MODE_F0_VERTICAL_RISING (0x62)
Name Bit(s) Access Description Reset
Reserved 31:16 - - -
F0 vertical rising 15:0 RW Specifies the line number given to the start of field 0's vertical blanking. 0x0

Did you find the information on this page useful?

Characters remaining:

Feedback Message