HDMI Intel® FPGA IP User Guide

ID 683798
Date 4/22/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.1.7. Sink Audio Decoder

The Audio Clock Regeneration packet transmits the CTS and N values required to synthesize the audio sample clock. The core also makes the CTS and N values available outside the core.

An audio clock synthesizer uses a phase-counter to recover the audio sample rate. The output from the audio clock synthesizer generates a valid pulse at the same rate as the audio sample clock from the attached source device. This valid pulse is available outside the core as an audio sample valid signal. This signal reads from a FIFO, which governs the rate of audio samples. The audio depacketizer drives the input to the FIFO.

The audio depacketizer extracts the 32-bit audio sample data from the incoming Audio Sample packets. The Audio Sample packets can hold from one to four sample data values. The audio format indicates the format of the received audio data as defined in Table 27.

The Audio InfoFrame and Audio Metadata packets are not used within the core. The packets are captured and presented outside the core. The bit fields (excluding control bit) are defined in Table 28, Table 29, Table 30, and Table 31 with reserved bits return 0.