6.5. Sink Deep Color Implementation When Support FRL = 0
ls_clk frequency = data rate per lane / effective transceiver width
vid_clk frequency = (data rate per lane / effective transceiver width) / color depth ratio
|Bits per Color||Color Depth Ratio|
When Support FRL = 0, the RX core uses the TMDS clock to drive the IOPLL reference clock. The IOPLL generates three output clocks that drive the CDR reference clock, ls_clk, and vid_clk.
When the HDMI RX core operates in vid_clk and ls_clk with the correct color depth ratio, the vid_valid signal is always high.
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