HDMI Intel® FPGA IP User Guide

ID 683798
Date 4/22/2022
Public

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6.1.17. I2C and EDID RAM Blocks

The HDMI IP includes a RAM to store your EDID information for the sink.

You need to specify your EDID content in a .mif or .hex file before you start generating the IP. You can also modify your EDID contents at run time.

The edid_ram_access signal acts as a trigger to the EDID RAM. When this signal is asserted, the IP holds the hpd signal low. During this period, you are free to modify the RAM content by accessing its Avalon memory-mapped interface through an Avalon memory-mapped master, such as NIOS.

After you are done modifying the RAM contents, deassert the edid_ram_access signal to reassert the hpd signal. The source device rereads the new EDID content.

Figure 58. Modifying EDID RAM

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