5.3. Source Clock Tree

HDMI Intel® FPGA IP User Guide

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Date 4/22/2022

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5.3. Source Clock Tree

The source uses various clocks.

Figure 33. Source Clock TreeThe figure shows how the different clocks connect in the source core.

For HDMI source, you must instantiate 4 transceiver channels: 3 channels to transmit data and 1 channel to transmit clock information.

Figure 34. Source Clock Tree when Support FRL = 1

When Support FRL =1, the transceiver PLL has two reference clocks:

Reference clock 0 supplied with arbitrary TMDS clock frequency from a programmable oscillator.
Reference clock 1 supplied with free running 100 MHz clock.

The transceiver PLL switches between reference clock 0 and reference clock 1 in TMDS and FRL modes.

A general purpose phase-locked loop (GPLL), that is referenced by a Transceiver Clock Out (tx_clk) clock is used to generate the FRL clock (frl_clk). You can fix the video clock (vid_clk) at a static frequency of 225 MHz. The link speed clock (ls_clk) is not required when you turn on the Support FRL parameter. Refer to Table 40 for more details.

Figure 35. Source Clock Tree when Support FRL =0

When Support FRL =0, the transceiver PLL in high-speed serial interface (HSSI) block only has one reference clock which supplied with arbitrary TMDS clock frequency from a programmable oscillator.

A general-purpose phase-locked loop (GPLL), that is referenced by same clock from the same programmable oscillator, is used to generate the video clock (vid_clk) and link speed clock (ls_clk). FRL clock (frl_clk) is not required when you turn off the Support FRL parameter.

The video data clocks into the core at vid_clk, the TMDS or FRL data clocks out from the core at tx_clk (Support FRL = 1) or ls_clk (Support FRL = 0), and the FRL data clocks with frl_clk.

If an application requires low TMDS Bit Rate (below the transceiver minimum data rate requirement), then the application needs a user logic consisting of a DCFIFO and oversampling logic.

The DCFIFO synchronizes the TMDS data from ls_clk to a faster transceiver output clock (tx_clk[0]). This DCFIFO is not required when Support FRL =1.
The oversampling logic repeats each bit of the TMDS data a given number of times.
When you enable the oversampling control bit, the transceiver transmits the TMDS data between the HDMI source core and the oversampling logic.
You can use tx_clk[0] across four channels if the transceiver is in bonding mode.

When Support FRL = 0, if an application does not require low TMDS Bit Rate, you can connect the core output directly to the transceiver with tx_clk[0] driving the core ls_clk. You do not require the GPLL to generate CLK1 (ls_clk).

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5.3. Source Clock Tree