HDMI Intel® FPGA IP User Guide

ID 683798
Date 4/22/2022
Public

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4.3.1.14.1. VIP Passthrough for HDMI Video Stream

For certain example designs, you can loop the video data output and synchronization signals from HDMI RX core through the VIP data path.

The Clocked Video Input II (CVI II) Intel® FPGA IP core converts clocked video formats to Avalon-ST video by stripping incoming clocked video of horizontal and vertical blanking, leaving only active picture data.

  • The IP core provides clock crossing capabilities to allow video formats running at different frequencies to enter the system.
  • The IP core also detects the format of the incoming clocked video and provides this information in a set of registers.
  • The Nios II processor uses this information to reconfigure the video frame mode registers of the CVO IP core in the VIP passthrough design.

The Video Frame Buffer II Intel® FPGA IP core buffers video frames into external RAM.

  • The IP core supports double and triple buffering with a range of options for frame dropping and repeating.
  • You can use the buffering options to solve throughput issues in the data path and perform simple frame rate conversion.

In a VIP passthrough design, you can reference the HDMI source PLL and sink PLL using separate clock sources. However, in a VIP bypass design, you must reference the HDMI source PLL and sink PLL using the same clock source.

The Clocked Video Output II (CVO II) Intel® FPGA IP core converts data from the flow-controlled Avalon-ST video protocol to clocked video.

  • The IP core provides clock crossing capabilities to allow video formats running at different frequencies to be created from the system.
  • It formats the Avalon-ST video into clocked video by inserting horizontal and vertical blanking and generating horizontal and vertical synchronization information using the Avalon-ST video control and active picture packets.
  • The video frame is described using the mode registers that are accessed through the Avalon-MM control port.
Table 18.  Difference between VIP Passthrough Design and VIP Bypass Design
VIP Passthrough Design VIP Bypass Design
  • Can reference the HDMI source PLL and sink PLL using separate clock sources
  • Demonstrates only certain video formats—640×480p60, 720×480p60, 1280×720p60, 1920×1080p60, and 3840×2160p24
  • Must reference the HDMI source PLL and sink PLL using the same clock source
  • Demonstrates all video formats.
Table 19.  VIP Passthrough and VIP Bypass Options for the Supported Devices
Device Family Symbols Per Clock HDMI Specification Support Bitec HDMI HSMC 2.0 Daughter Card Directory VIP Passthrough VIP Bypass
Arria V 2 1.4b HSMC (Rev8) av_sk Supported Supported
4 2.0b HSMC (Rev8) av_sk_hdmi2 Not supported Supported
Stratix V 2 2.0b HSMC (Rev8) sv_hdmi2 Not supported Supported

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