HDMI Intel® FPGA IP User Guide

ID 683798
Date 4/22/2022
Public

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9.1.1.13. VSI_PACKET_DATA1 (0x10)

Refer to HDMI Specification 1.4b Section 8.2.3 HDMI Vendor Specific InfoFrame for the details of each field.

Table 77.  VSI_PACKET_DATA1 (0x10)
Name Bit(s) Access Description Reset
Reserved 31:24 - - -
VSI packet byte6 23:16 RW VSI packet data byte 6.

When HDMI video format set to 0x03 and 3D structure is 0x9 - 0xF:

VSI packet data byte 6 [7:4]: 3D_Ext_Data

VSI packet data byte 6 [3:0]: 3D_Ext_Data

0x0
VSI packet byte5 15:8 RW VSI packet data byte 5.

When HDMI video format =0x1:

VSI packet data byte 5 [7:0]: HDMI VIC

When HDMI video format = 0x02,

VSI packet data byte 5 [7:4]: 3D Structure

VSI packet data byte 5 [3:0]: Reserved

0x0
VSI packet byte4 7:0 RW VSI packet data byte 4.

[7:5]: HDMI Video Format

[4:0] Reserved

0x0

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