HDMI Intel® FPGA IP User Guide

ID 683798
Date 4/22/2022
Public

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7.2. HDMI Sink Parameters

Table 63.  HDMI Sink Parameters
Parameter Value Description
Device family
  • Intel® Agilex™ F-tile
  • Intel® Stratix® 10
  • Intel® Arria® 10
  • Intel® Cyclone® 10 GX
  • Arria V
  • Stratix V
Targeted device family. This parameter inherits the value from the project device.
Direction

Transmitter

Receiver

Select HDMI receiver.
Pixels per clock 2 or 8 pixels per clock

Determines how many pixels are processed per clock.

  • When you turn off Support FRL, supports 2 pixels per clock.
  • When you turn on Support FRL, supports 8 pixels per clock.
Note: This parameter is available only with Intel® Arria® 10 and Intel® Stratix® 10 devices.
Transceiver width 20 or 40 bits Determines the required transceiver width. The transceiver width depends on the number of TMDS symbols processed in parallel (symbols per clock).
  • When you turn off Support FRL, transceiver width is 20 bits (2 symbols per clock).
  • When you turn on Support FRL, transceiver width is 40 bits (4 symbols per clock).
Note: This parameter is available only with Intel® Arria® 10 and Intel® Stratix® 10 devices.
Enable active video protocol AXIS-VVP Full, None Determines the input video data format. When set to AXIS-VVP full, the video input follows the AXI streaming VVP full specification (**link to vvp spec**). When set to None, the video input is in clocked video format.
Support auxiliary On, Off Determines if auxiliary channel encoding is included. This parameter is turned on by default.

This parameter is always turned on when Support FRL is enabled.

Support deep color On, Off

Determines if the core can encode deep color formats. This parameter is turned on by default.

Support audio On, Off

Determines if the core can encode audio data.

To enable this parameter, you must also enable the Support auxiliary parameter. This parameter is turned on by default.

Support FRL On, Off

Turn on to enable the FRL path.

When enabled, the clock domains for the auxiliary and audio ports, and the internal modules are different Refer to the block diagram for more details.

Note: This parameter is available only with Intel® Arria® 10 and Intel® Stratix® 10 devices.
Support HDCP 1.4 On, Off

Turn on to enable HDCP 1.4 RX support. This parameter can only be used with Intel® Arria® 10 and Intel® Stratix® 10 devices.

Note: The HDCP-related parameters are not included in the Intel® Quartus® Prime Pro Edition software. To access the HDCP feature, contact Intel at https://www.intel.com/content/www/us/en/broadcast/products/programmable/applications/connectivity-solutions.html.
Support HDCP 2.3 On, Off

Turn on to enable HDCP 2.3 RX support. This parameter can only be used with Intel® Arria® 10 and Intel® Stratix® 10 devices.

Note: The HDCP-related parameters are not included in the Intel® Quartus® Prime Pro Edition software. To access the HDCP feature, contact Intel at https://www.intel.com/content/www/us/en/broadcast/products/programmable/applications/connectivity-solutions.html.
Support HDCP Key Management On, Off Turn on to enable HDCP key management support. You can only turn on this parameter if you turn on the Support HDCP 1.4 or Support HDCP 2.3 parameters.
Note:
  1. The HDCP-related parameters are not included in the Intel Quartus Prime Pro Edition software. To access the HDCP feature, contact Intel at https://www.intel.com/content/www/us/en/broadcast/products/programmable/applications/connectivity-solutions.html.
  2. The HDCP key management support from version 21.3 onwards is not compatible with the KEYENC version 21.2 and earlier. You need to re-encrypt the HDCP production keys using the KEYENC version 21.3 onwards. Refer to HDMI Intel Arria 10 FPGA IP Design Example User Guide and HDMI Intel Stratix 10 FPGA IP Design Example User Guide for more details.
Manufacturer OUI

The Manufacturer Organizationally Unique Identifier (OUI) assigned to the manufactured device to be written into the SCDC registers of address 0xD0, 0xD1, and 0xD2.

Key in 3 byte hexadecimal data.

Device ID String

The Device Identification (ID) string to be written into the SCDC registers from addresses 0xD3 to 0xDa.

Use this parameter to identify the sink device. You can key in up to eight ASCII characters. If you use less than eight characters, the unused bytes are set to 0x00.

Hardware Revision

Indicates the major and minor revisions of the hardware. Key in one byte of integer data.

  • Upper byte represents major revision.
  • Lower byte represents minor revision.

The hardware major revision increments on a major silicon or board revision. The hardware minor revision increments on a minor silicon revision or minor board revision and resets to 0 when the major revision increments.

Include I2C slave On, Off

Turn on to include a pair of I2C slaves for EDID and SCDC registers. path.

Include EDID RAM On, Off

Turn on to include RAM to store EDID information for RX.

Note: You can only turn on this parameter if you turned on the Include I2C slave parameter.
EDID RAM size In multiple of 2N

Specifies the memory size in number of N-bit words. The value must be in multiple of 2N.

For example, the default memory size is 256 words which is 28 with N = 8.

The N also determines the width of the address bus of the RAM’s Avalon® memory-mapped interface.

Note: This parameter is enabled only if you turned on the Include EDID RAM parameter.
RAM file path

Initial content of the memory. The file must be in .hex or .mif file type.

Note: This parameter is enabled only if you turned on the Include EDID RAM parameter.
HPD signal polarity 0, 1 Specifies the polarity of Hot Plug Detect (HPD) signal from the connector.
  • 0: Negative
  • 1: Positive
Note: For Bitec daughter card, always set the polarity to 0.
Include I2C Master/Slave On, Off

Turn on to include I2C master on the HDMI TX or I2C slave on the HDMI RX for the DDC channel communication.

When enabled for RX, HDMI RX core includes I2C slave with I2C serial interface exposed for the connection to the HDMI connector. I2C slave is driven internally by EDID RAM and SCDC register.

When enabled for TX, HDMI TX core includes I2C master with I2C serial interface exposed for the connection to the HDMI connector. I2C master will also expose Avalon-MM interface for the user control using NIOS.

When Enable Active Video Protocol is set to AXIS-VVP Full, Advanced Configuration tab appears in the HDMI sink GUI. Advanced Configuration tab contains the parameter below.

Parameter Value Description
Video in and out use the same clock On, Off
  • When SUPPORT_FRL=1, set this parameter to On. The CV2AXI core input and output are driven by the same clock source. Drive axi4s_clk and vid_clk with the same fixed clock frequency. The clock frequency must be equal or greater than 225 MHz.
  • When SUPPORT_FRL=0, set this parameter to Off. Drive the vid_clk frequency = data rate per lane / transceiver width / color depth ratio. Drive axi4s_clk to a fixed clock frequency. The axi4s_clk clock frequency must be equal or greater than the vid_clk.
    Note: SUPPORT_FRL=0 is not supported when Active Video Protocol = AXIS-VVP Full for now.
Enable user-defined packet support On, Off
  • When set to On, user defined packet support is enabled. You can retrieve auxiliary data through the user packet register configuration using host processor.
  • When set to Off, user defined packet support is disabled.
Enable AXIS auxiliary packet interface On, Off
  • When set to On, AXI4-stream auxiliary packet interface is enabled. You can receive auxiliary data through AXI4-stream auxiliary packet interface.
  • When set to Off, AXI4-stream auxiliary packet interface support is disabled.

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