6.1.10. HDCP 2.3 RX Architecture

HDMI Intel® FPGA IP User Guide

Download PDF

ID 683798

Date 4/22/2022

Version

Public

A newer version of this document is available. Customers should click here to go to the newest version.

Visible to Intel only — GUID: btm1559227494617

Ixiasoft

View Details

6.1.10. HDCP 2.3 RX Architecture

The receiver block decrypts the protected video and auxiliary data from the connected HDCP 2.3 device. The HDCP 2.3 receiver block has identical structure layers as the HDCP 2.3 transmitter block.

Figure 56. Architecture Block Diagram of HDCP 2.3 RX IP

The HDCP 2.3 RX core is fully autonomous. For HDMI application, the transmitter drives the HDCP 2.3 RX core using the standard DDC interface supporting I²C protocol.

The HDCP specifications requires the HDCP 2.3 RX core to be programmed with the DCP-issued production key – Global Constant (lc128), RSA private key (kprivrx) and RSA Public Key Certificate (certrx). The IP retrieves the key from the on-chip memory externally to the core through the HDCP Key Port. The on-chip memory must store the key data in the arrangement shown in the table below.

Table 57. HDCP 2.3 RX Key Port Addressing
Address	Content
8'hE3	lc128[127:96]
8'hE2	lc128[95:64]
8'hE1	lc128[63:32]
8'hE0	lc128[31:0]
8'hDF	kprivrx_p[511:480]
...	...
8'hD0	kprivrx_p[31:0]
8'hCF	kprivrx_q[511:480]
...	...
8'hC0	kprivrx_q[31:0]
8'hBF	kprivrx_dp[511:480]
...	...
8'hB0	kprivrx_dp[31:0]
8'hAF	kprivrx_dq[511:480]
...	...
8'hA0	kprivrx_dq[31:0]
8'h9F	kprivrx_qinv[511:480]
...	...
8'h90	kprivrx_qinv[31:0]
8'h83–8'h8F	Reserved
8'h82	{16’d0, certrx[4175:4160]}
8'h81	certrx[4159:4128]
...	...
8'h01	certrx[63:32]
8'h00	certrx[31:0]

The Video Stream and Auxiliary Layer receives audio and video content over its Video and Aux Data Input Port, and performs the decryption operation. The Video Stream and Auxiliary Layer detects the Encryption Status Signaling (ESS) provided by the HDMI IP to determine when to decrypt frames.

To implement the HDCP 2.3 RX core as a repeater upstream interface, the IP must propagate certain information such as ReceiverID List and RxInfo to the upstream transmitter and to be used for HMAC computation. The repeater downstream interface (TX) must provide this information using the Repeater Message Port (Avalon-MM). You can use the same clock source to drive the clocking for the HDCP Register Port and Repeater Message Port.

The RX registers mapping defined in the following table is equivalent to the address space for HDCP 2.3 receiver defined in the HDCP specification.

Table 58. HDCP 2.3 RX Registers Mapping
Address	Register	R/W	Reset	Bit	Bit Name	Description
0x44 – 0x4F	Rsvd	RO	0x00	7:0	Reserved	Reserved.
0x50	`HDCP2VERSION`	RO	0x04	7:3	Reserved	Reserved.
				2	`HDCP22`	When set to 1, the core supports HDCP 2.2 and above.
				1:0	Reserved	Reserved.
0x51 – 0x5F	Rsvd	RO	0x00	7:0	Reserved	Reserved.
0x60	`WRITE_MESSAG`E	WO	0x00	7:0	`WR_MSG`	Variable length message written by the transmitter as a single burst write to this address.
0x61 – 0x6F	Rsvd	RO	0x00	7:0	Reserved	Reserved.
0x70	`RXSTATUS0`	RO	0x00	7:0	`MSG_SIZE0`	The lower part of message size in bytes available at the receiver for reading by the transmitter.
0x71	`RXSTATUS1`	RO	0x00	7:4	Reserved	Reserved
				3	`REAUTH_REQ`	When set to 1, indicates the link integrity check failure at the receiver (including upstream side of the repeater) or the upstream side of the repeater has transitioned into an unauthenticated state. Self-cleared by the core on every new authentication initiated by the AKE_Init message.
				2	`READY`	When set to 1, the repeater has built the list of downstream Receiver IDs and computed the verification value V’. Self-cleared by the core as soon as the RepeaterAuth_Send_ReceiverID_List message has been read by the transmitter or on every new authentication request by the transmitter.
				1:0	`MSG_SIZE1`	The upper part of message size in bytes available at the receiver for reading by the transmitter.
0x72 – 0x7F	Rsvd	RO	0x00	7:0	Reserved	Reserved.
0x80	`READ_MESSAGE`	RO	0x00	7:0	`RD_MSG`	Variable length message read by the transmitter as a single burst read from this address.
0x81 – 0xBF	Rsvd	RO	0x00	7:0	Reserved	Reserved.
0xC0 – 0xFF	DBG	RW	0x00	7:0	`DBG_REGS`	Implemented specific debug registers.

Table 59. HDCP 2.3 RX Repeater Registers Mapping
Address	Register	R/W	Reset	Bit	Bit Name	Description
0x00	`RPT_RCVDID_LIST`	WO	0x00000000	31:8	Reserved	Reserved
0x00	`RPT_RCVDID_LIST`	WO	0x00000000	7:0	`RCVDID_LIST`	Byte write ReceiverID_List in big endian order.
0x01	`RPT_RXINFO`	RW	0x00000000	31:19	Reserved	Reserved
				18	`REQUEST`	Read-only. Asserted by the core to request for `RCVDID_LIST` and `RXINFO.` This usually happens when re-authentication is triggered by the connected upstream. Note that when `REQUEST` is asserted, the `READY` should also be asserted.
				17	`READY`	Read-only. Asserted by the core to indicate `RCVDID_LIST` and `RXINFO` are processed. Write `RCVDID_LIST` and `RXINFO` after this bit is asserted.
				16	`VALID`	Set to 1 after `RCVDID_LIST` and `RXINFO` are written. Self-cleared by the core after `RCVDID_LIST` and `RXINFO` are read.
				15:0	`RXINFO`	[15:12]: Reserved. [11:9]: `DEPTH` [8:4]: `DEVICE_COUNT` [3]: `MAX_DEVS_EXCEEDED` [2]: `MAX_CASCADE_EXCEEDED` [1]: `HDCP2_REPEATER_DOWNSTREAM` [0]: `HDCP1_DEVICE_DOWNSTREAM`
0x02	`RPT_TYPE`	RO	0x00000000	31:9	Reserved	Reserved
				8	`VALID`	Asserted by the core to indicate content stream `TYPE` is valid. Self-cleared by the core after `TYPE` is read.
				7:0	`TYPE`	0x00: Type 0 Content Stream 0x01: Type 1 Content Stream 0x02-0xFF: Reserved. Treated as Type 1 Content Stream.
0x03	`RPT_MISC`	RW	0x00000000	31:1	Reserved	Reserved.
0x03	`RPT_MISC`	RW	0x00000000	0	`REPEATER`	Set to 0 if no downstream is connected or if the connected downstream is not HDCP 2.3-capable. This means the receiver IP core is an end-point receiver rather than a repeater. Set to 1 if the connected downstream is HDCP- capable.

Select Your Language

Using Intel.com Search

Quick Links

Recent Searches

Advanced Search

Only search in

HDMI Intel® FPGA IP User Guide

6.1.10. HDCP 2.3 RX Architecture