HDMI Intel® FPGA IP User Guide

ID 683798
Date 4/22/2022

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Document Table of Contents STATUS_CONTROL (0x00)

Table 65.  STATUS_CONTROL (0x00)
Name Bit(s) Access Description Reset
Reserved 31:9 - Reserved -
Hotplug detect 18 RO Indicates hotplug detect pin current status

1'b1: HPD high-level

1'b0: HPD low-level

TMDS ratio 17 RW TMDS bit to clock ratio

1'b0: 1/10

1'b1: 1/40

Reserved 16:10 - Reserved -
AVMute clear 9 RW Set to 1'b1 to send a GCP packet with clear AVMUTE bit set 0x0
AVMute set 8 RW Set to 1'b1 to send a GCP packet with set AVMUTE bit set 0x0
Reserved 7-6 - Reserved -
HDMI mode 5 RW Set to 1'b0 to enable DVI mode.

Set to 1'b1 to enable HDMI mode.

Reserved 4:0 - Reserved -