HDMI Intel® FPGA IP User Guide

ID 683798
Date 4/22/2022
Public

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9.1.1.2. IRQ_STATUS (0x01)

Table 66.  IRQ_STATUS (0x01)
Name Bit(s) Access Description Reset
Reserved 31:4 - - -
Video overflow 3 W1C Indicates if the FIFO clocking the data from the video path to the FRL path is overflowing.

Applicable only for FRL mode.

0x0
Hotplug detect 2 W1C Indicates the status of the hotplug detect (HPD) input 0x0
Reserved 1:0 - - -

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