HDMI Intel® FPGA IP User Guide

ID 683798
Date 4/22/2022
Public

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8.1. Simulation Walkthrough

Setting up and running the HDMI simulation example consists of two steps.
Note: This simulation flow applies only to Intel® Quartus® Prime Standard Edition using ModelSim* - Intel® FPGA Starter Edition. For Intel® Quartus® Prime Pro Edition flow, refer to the respective Design Example User Guides.
Note: When I2C Master/Slave parameter is turned on, simulation design example is not supported.
  1. Copy the simulation files from <IP root directory>/altera/altera_hdmi/sim_example to your working directory.
  2. Generate the IP simulation files and scripts, compile, and simulate.
    1. Start the Nios II Command Shell.
    2. Type the command below and enter.
      sh runall.sh
      This script executes the following commands:
      Command  
      Generate the simulation files for the HDMI cores.
      • ip-generate --project-directory=./ --component-file=./hdmi_rx_single.qsys --output-directory=./hdmi_rx_single/sim/ --file-set=SIM_VERILOG --report-file=sopcinfo:./hdmi_rx_single.sopcinfo --report-file=html:./hdmi_rx_single.html --report-file=spd:./hdmi_rx_single/sim/hdmi_rx_single.spd --report-file=qip:./hdmi_rx_single/sim/hdmi_rx_single.qip
      • ip-generate --project-directory=./ --component-file=./hdmi_rx_double.qsys --output-directory=./hdmi_rx_double/sim/ --file-set=SIM_VERILOG --report-file=sopcinfo:./hdmi_rx_double.sopcinfo --report-file=html:./hdmi_rx_double.html --report-file=spd:./hdmi_rx_double/sim/hdmi_rx_double.spd --report-file=qip:./hdmi_rx_double/sim/hdmi_rx_double.qip
      • ip-generate --project-directory=./ --component-file=./hdmi_tx_single.qsys --output-directory=./hdmi_tx_single/sim/ --file-set=SIM_VERILOG --report-file=sopcinfo:./hdmi_tx_single.sopcinfo --report-file=html:./hdmi_tx_single.html --report-file=spd:./hdmi_tx_single/sim/hdmi_tx_single.spd --report-file=qip:./hdmi_tx_single/sim/hdmi_tx_single.qip
      • ip-generate --project-directory=./ --component-file=./hdmi_tx_double.qsys --output-directory=./hdmi_tx_double/sim/ --file-set=SIM_VERILOG --report-file=sopcinfo:./hdmi_tx_double.sopcinfo --report-file=html:./hdmi_tx_double.html --report-file=spd:./hdmi_tx_double/sim/hdmi_tx_double.spd --report-file=qip:./hdmi_tx_double/sim/hdmi_tx_double.qip
      Merge the four resulting msim_setup.tcl scripts to create a single mentor/msim_setup.tcl script. ip-make-simscript --spd=./hdmi_tx_single/sim/hdmi_tx_single.spd --spd=./hdmi_tx_double/sim/hdmi_tx_double.spd --spd=./hdmi_rx_single/sim/hdmi_rx_single.spd --spd=./hdmi_rx_double/sim/hdmi_rx_double.spd
      Compile and simulate the design in the ModelSim software. vsim -c -do msim_hdmi.tcl
      Generate the simulation files for the HDMI cores.  
      Merge the resulting msim_setup.tcl scripts to create a single mentor/msim_setup.tcl script.  
      Compile and simulate the design in the ModelSim software.  
    Example successful result:
    # SYMBOLS_PER_CLOCK = 4
    # VIC = 0
    # AUDIO_CLK_DIVIDE = 800
    # TEST_HDMI_6G = 1
    # Simulation pass
    # ** Note: $finish : bitec_hdmi_tb.v (647)
         Time: 15702552 ns Iteration: 3 Instance: /bitec_hdmi_tb
    # End time: 14:39:02 on Feb 04,2016, Elapsed time: 0:03:17
    # Errors: 0, Warnings: 134

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