HDMI Intel® FPGA IP User Guide

ID 683798
Date 4/22/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents VIDEO_MODE_F1_LINE_COUNT (0x57)

Table 106.  VIDEO_MODE_F1_LINE_COUNT (0x57)
Name Bit(s) Access Description Reset
Reserved 31:16 - - -
F1 line count 15:0 RW Specifies the active picture height of interlaced video field 1. 0x0