HDMI Intel® FPGA IP User Guide

ID 683798
Date 4/22/2022
Public

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4.3.1.10. Transceiver Native PHY (TX)

The Arria V and Stratix V Transceiver Native PHY (TX) configuration settings are typically the same as RX.

Table 16.  Arria V and Stratix V Transceiver Native PHY (TX) Configuration Settings (6,000 Mbps)This table shows an example of Arria V and Stratix V Transceiver Native PHY (TX) configuration settings for TMDS bit rate of 6,000 Mbps.
Parameters Settings
Datapath Options
Enable TX datapath On
Enable RX datapath Off
Enable Standard PCS On
Initial PCS datapath selection Standard
Number of data channels 4
Bonding mode xN
Enable simplified data interface On
TX PMA
Data rate 6,000 Mbps
TX local clock division factor 1
Enable TX PLL dynamic reconfiguration On
Use external TX PLL Off
Number of TX PLLs 1
Main TX PLL logical index 0
Number of TX PLL reference clocks 1
PLL type CMU
Reference clock frequency 600 MHz
Selected reference clock source 0
Selected clock network xN
Standard PCS
Standard PCS protocol Basic
Standard PCS/PMA interface width
  • 10 (for 1 symbol per clock)
  • 20 (for 2 and 4 symbols per clock)
Enable TX byte serializer
  • Off (for 1 and 2 symbols per clock)
  • On (for 4 symbols per clock)
Table 17.  Arria V and Stratix V Transceiver Native PHY (TX) Common Interface PortsThis table describes the Arria V and Stratix V Transceiver Native PHY (TX) common interface ports.
Signals Direction Description
Clocks
tx_pll_refclk Input

The reference clock input to the TX PLL.

tx_std_clkout[3:0] Output

TX parallel clock output.

tx_std_coreclkin[3:0] Input

TX parallel clock that drives the write side of the TX phase compensation FIFO.

Connect to tx_std_clkout[0] ports.

Resets
tx_analogreset[3:0] Input

When asserted, resets all the blocks in TX PMA.

Connect to Transceiver PHY Reset Controller (TX) IP core.

tx_digitalreset[3:0] Input

When asserted, resets all the blocks in TX PCS.

Connect to the Transceiver PHY Reset Controller (TX) IP core.

TX PLL
pll_powerdown Input

When asserted, resets the TX PLL.

Connect to the Transceiver PHY Reset Controller (TX) IP core.

pll_locked Output

When asserted, indicates that the TX PLL is locked.

Connect to the Transceiver PHY Reset Controller (TX) IP core.

PCS Ports
unused_tx_parallel_data Input Leave unconnected.
tx_parallel_data[S*4*10-1:0] Input PCS TX parallel data.
Note: S=Symbols per clock.
PMA Port
tx_serial_data[3:0] Output TX differential serial output data.
Calibration Status Port
tx_cal_busy[3:0] Output When asserted, indicates that the initial TX calibration is in progress. This port is also asserted if the reconfiguration controller is reset. Connect to the Transceiver PHY Reset Controller (TX) IP core.
Reconfiguration Ports
reconfig_to_xcvr[349:0] Input Reconfiguration signals from the Transceiver Reconfiguration Controller.
reconfig_from_xcvr[229:0] Output Reconfiguration signals to the Transceiver Reconfiguration Controller.

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