HDMI Intel® FPGA IP User Guide

ID 683798
Date 4/22/2022
Public

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9.3.1. HDMI Sink Register Summary

Table 121.  HDMI Sink Register Summary
Base Address 0x400
Address Register Description
0x01 STATUS Indicates HDMI RX status, including cable detect, alignment lock, video lock, TMDS ratio, scrambler enabled, AV muted and LTS state.

Refer to Table: STATUS (0x01).

0x02 IRQ_STATUS HDMI RX interrupt for all the status bit.

Refer to Table: IRQ_STATUS (0x02).

0x03 IRQ_MASK HDMI RX interrupt mask for all the status bit.

Refer to Table: IRQ_ MASK (0x03).

0x04 HOTPLUG Indicates HDMI RX hotplug detect.

Refer to Table: HOTPLUG (0x04).

0x05 LINK_MODE Indicates received video link mode, whether HDMI or DVI mode is received.

Refer to Table: LINK_MODE (0x05).

0x06 VIDEO_COLOUR Indicates received video colour depth and colour encoding.

Refer to Table: VIDEO_COLOUR (0x06).

0x0C AVI_PACKET_DATA0 HDMI RX AVI packet bye 0-3.

Refer to Table: AVI_PACKET_DATA0 (0x0C).

0x0D AVI_PACKET_DATA1 HDMI RX AVI packet bye 4-7.

Refer to Table: AVI_PACKET_DATA1 (0x0D).

0x0E AVI_PACKET_DATA2 HDMI RX AVI packet bye 8-11.

Refer to Table: AVI_PACKET_DATA2 (0x0E).

0x0F AVI_PACKET_DATA3 HDMI RX AVI packet bye 12-14.

Refer to Table: AVI_PACKET_DATA3 (0x0F).

0x10 USER_PACKET_FILTER HDMI RX user packet filter, for user to select user data packets to be captured.

Refer to Table: USER_PACKET_FILTER (0x10).

0x11 USER_BUFFER_STATUS_CONTROL Indicates HDMI RX user buffer status, including buffer empty or full, last data is read and valid data present in the buffer. You can also set bit in this register to empty the data buffer.

Refer to Table: USER_BUFFER_STATUS_CONTROL (0x11).

0x12 USER_BUFFER_LEVEL Indicates HDMI RX user buffer level.

Refer to Table: USER_BUFFER_LEVEL (0x12).

0x13 USER_BUFFER_DATA Contains HDMI RX user buffer data.

Refer to Table: USER_BUFFER_DATA (0x13).

0x14 AUX_PACKET_FILTER HDMI RX auxiliary packet filter, for you to select auxiliary data packets to be filter at auxiliary interface.

Refer to Table: AUX_PACKET_FILTER (0x14).

0x21 AUDIO_INFOFRAME_PACKET_DATA0 HDMI RX audio inforframe first data, including checksum, channel count, audio format type, bits-per-audio sample, sampling frequency, audio format type.

Refer to Table: AUDIO_INFOFRAME_PACKET_DATA0 (0x21).

0x22 AUDIO_INFOFRAME_PACKET_DATA1 HDMI RX audio inforframe second data, including channel allocation, LFE playback level information, level shift information and down-mix inhibit flag.

Refer to Table: AUDIO_INFOFRAME _PACKET_DATA1 (0x22).

0x25 AUDIO_METADATA_PACKET_HEADER HDMI RX audio metadata packet header byte 0-2.

Refer to Table: AUDIO_METADATA _PACKET_HEADER (0x25).

0x26 AUDIO_METADATA_PACKET_DATA0 HDMI RX audio metadata packet data byte 0-3.

Refer to Table: AUDIO_METADATA _PACKET_DATA0 (0x26).

0x27 AUDIO_METADATA_PACKET_DATA1 HDMI RX audio metadata packet data byte 4-6.

Refer to Table: AUDIO_METADATA _PACKET_DATA1 (0x27).

0x28 AUDIO_METADATA_PACKET_DATA2 HDMI RX audio metadata packet data byte 7-10.

Refer to Table: AUDIO_METADATA _PACKET_DATA2 (0x28).

0x29 AUDIO_METADATA_PACKET_DATA3 HDMI RX audio metadata packet data byte 11-13.

Refer to Table: AUDIO_METADATA _PACKET_DATA3 (0x29).

0x2A AUDIO_METADATA_PACKET_DATA4 HDMI RX audio metadata packet data byte 14-17.

Refer to Table: AUDIO_METADATA _PACKET_DATA 4 (0x2A).

0x2B AUDIO_METADATA_PACKET_DATA5 HDMI RX audio metadata packet data byte 18-19.

Refer to AUDIO_METADATA _PACKET_DATA5 (0x2B).

0x2C VSI_PACKET_DATA0 HDMI RX VSI packet byte 0-3.

Refer to Table: VSI_PACKET_DATA0 (0x2C).

0x2D VSI_PACKET_DATA1 HDMI RX VSI packet byte 4-7.

Refer to Table: VSI_PACKET_DATA0 (0x2C).

0x2E SCDC_FRL_STATUS HDMI RX SCDC FRL status, including FRL locked, FRL rate and FFE levels.

Refer to Table: SCDC_FRL_STATUS (0x2E).

0x2F SCDC_FRL_CONTROL HDMI RX SCDC FRL control, for you to set FLT ready flag, source test configuration and link training patter in the sink SCDC register.

Refer to Table: SCDC_FRL_CONTROL (0x2F).

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