HDMI Intel® FPGA IP User Guide

ID 683798
Date 4/22/2022

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Document Table of Contents

6.1.11. FRL Depacketizer

FRL depacketizer reconstructs the FRL packets into HDMI data.

FRL depacketizer contains a mixed-width DCFIFO to clock the data from the frl_clk domain to the vid_clk domain. This block also demaps the HDMI data from number of FRL characters per clock * 16 bits to pixels per clock * 24 bits, where number of FRL characters per clock is always 16 and pixels per clock is always 8 in FRL mode.