HDMI Intel® FPGA IP User Guide

ID 683798
Date 4/22/2022
Public

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Document Table of Contents

2. HDMI Overview

The HDMI Intel® FPGA IP provides support for next generation video display interface technology.
The HDMI standard specifies a digital communications interface for use in both internal and external connections:
  • Internal connections—interface within a PC and monitor
  • External display connections—interface between a PC and monitor or projector, between a PC and TV, or between a device such a DVD player and TV display.

The HDMI system architecture consists of sinks and sources. A device may have one or more HDMI inputs and outputs.

The HDMI cable and connectors carry four differential pairs that make up the Transition Minimized Differential Signaling (TMDS) data and clock channels for HDMI 1.4 and HDMI 2.0. For HDMI 2.1, HDMI cable and connectors carry four fixed rate link (FRL) lanes of data. You can use these channels to carry video, audio, and auxiliary data.

The HDMI also carries a Video Electronics Standards Association (VESA) Display Data Channel (DDC) and Status and Control Data Channel (SCDC). The DDC configures and exchanges status between a single source and a single sink. The source uses the DDC to read the sink's Enhanced Extended Display Identification Data (E-EDID) to discover the sink's configuration and capabilities.

The optional Consumer Electronics Control (CEC) protocol provides high-level control functions between various audio visual products in your environment.

The optional HDMI Ethernet and Audio Return Channel (HEAC) provides Ethernet compatible data networking between connected devices and an audio return channel in the opposite direction of TMDS. The HEAC also uses Hot-Plug Detect (HPD) line for link detection.

Figure 1.  HDMI Intel® FPGA IP Block Diagram for TMDS ModeThe figure below illustrates the blocks in the HDMI Intel® FPGA IP for TMDS Mode.

Based on TMDS encoding, the HDMI protocol allows the transmission of both audio and video data between source and sink devices.

An HDMI interface consists of three color channels accompanied by a single clock channel. You can use each color line to transfer both individual RGB colors and auxiliary data.

Note: Refer to AN 837: Design Guidelines for Intel FPGA HDMI to know more about the channel mapping to the RGB colors for HDMI 1.4 and HDMI 2.0.

The receiver uses the TMDS clock as a frequency reference for data recovery on the three TMDS data channels. This clock typically runs at the video pixel rate.

TMDS encoding is based on an 8-bit to 10-bit algorithm. This protocol attempts to minimize data channel transition, and yet maintain sufficient transition so that a sink device can lock reliably to the data stream.

Figure 2. Fixed Rate Link (FRL)

In HDMI 1.4 and HDMI 2.0, 3 lanes carry data and 1 lane carries TMDS clock. When operating in FRL mode, the clock channel carries data as well. As the HDMI 2.1 specification requires backward compatibility with HDMI 1.4 and HDMI 2.0, you need to configure the 4th lane to carry data or clock during run time.

You can configure the FRL mode to 3 lanes and 4 lanes. In 3-lane FRL mode, each lane can operate at 3 Gbps or 6 Gbps. In 4-lane FRL mode, each lane can operate at 6 Gbps, 8 Gbps, 10 Gbps, or 12 Gbps.

Use category 3 (Cat 3) cable for FRL mode to ensure good signal integrity.

Figure 3.  HDMI Intel® FPGA IP Video Stream Data
The figure above illustrates two data streams:
  • Data stream in green—transports color data
  • Data stream in dark blue—transports auxiliary data
Table 2.  Video Data and Auxiliary DataThe table below describes the function of the video data and auxiliary data.
Data Description
Video data
  • Packed representation of the video pixels clocked at the source pixel clock.
  • Encoded using the TMDS 8-bit to 10-bit algorithm.
Auxiliary data
  • Transfers audio data together with a range of auxiliary data packets.
  • Sink devices use auxiliary data packets to correctly reconstruct video and audio data.
  • Encoded using the TMDS Error Reduction Coding–4 bits (TERC4) encoding algorithm.

Each data stream section is preceded with guard bands and pre-ambles. The guard bands and pre-ambles allow for accurate synchronization with received data streams.

The following figures show the arrangement of the video data, video data enable, video H-SYNC, and video V-SYNC in 1, 2, 4, and 8 pixels per clock.

Figure 4. Video Data, Video Data Valid, H-SYNC, and V-SYNC—1 Pixel per Clock
Figure 5. Video Data, Video Data Valid, H-SYNC, and V-SYNC—2 Pixels per Clock
Figure 6. Video Data, Video Data Valid, H-SYNC, and V-SYNC—4 Pixels per Clock
Figure 7. Video Data, Video Data Valid, H-SYNC, and V-SYNC—8 Pixels per Clock

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