HDMI Intel® FPGA IP User Guide

ID 683798
Date 4/22/2022

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Document Table of Contents Source General Control Packet (GCP)

Table 23.  Source GCP Bit-FieldsThis table lists the controllable bit-fields for the Source gcp[5:0] port.
Bit Field Name Value Comment
gcp[3:0] Color Depth (CD) CD3 CD2 CD1 CD0 Color depth
0 0 0 0 Color depth not indicated
0 1 0 0 8 bpc or 24 bits per pixel (bpp)
0 1 0 1 10 bpc or 30 bpp
0 1 1 0 12 bpc or 36 bpp
0 1 1 1 16 bpc or 48 bpp
Others Reserved
gcp[4] Set_AVMUTE Refer to HDMI 1.4b Specification Section 5.3.6.
gcp[5] Clear_AVMUTE Refer to HDMI 1.4b Specification Section 5.3.6.
All other fields for the source GCP, (for example, Pixel Packing Phase and Default Phase as described in HDMI 1.4b Specification Section 5.3.6) are calculated automatically inside the core. You must provide the bit-field values in the table above through the source gcp[5:0] port. The GCP on the Auxiliary Data Port will always be filtered.