HDMI Intel® FPGA IP User Guide

ID 683798
Date 4/22/2022
Public

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9.1.1.24. AUDIO_INFOFRAME_CONTROL (0x20)

Table 87.  AUDIO_INFOFRAME_CONTROL (0x20)
Name Bit(s) Access Description Reset
Reserved [31:1] - - -
Audio info disable 0 RW When set to 1, HDMI TX core does not send the audio infoframe from HDMI TX AUDIO_INFOFRAME_PACKET_DATA registers .

When set to 0, HDMI TX core sends the audio infoframe from HDMI TX AUDIO_INFOFRAME_PACKET_DATA registers.

0x0

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