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1. HDMI Intel® FPGA IP Quick Reference
2. HDMI Overview
3. HDMI Intel® FPGA IP Getting Started
4. HDMI Hardware Design Examples
5. HDMI Source
6. HDMI Sink
7. HDMI Parameters
8. HDMI Simulation Example
9. Registers
10. HDMI Intel® FPGA IP User Guide Archives
11. Document Revision History for the HDMI Intel® FPGA IP User Guide
4.3.1.1. Transceiver Native PHY (RX)
4.3.1.2. PLL Intel FPGA IP Cores
4.3.1.3. PLL Reconfig Intel FPGA IP Core
4.3.1.4. Multirate Reconfig Controller (RX)
4.3.1.5. Oversampler (RX)
4.3.1.6. DCFIFO
4.3.1.7. Sink Display Data Channel (DDC) & Status and Control Data Channel (SCDC)
4.3.1.8. Transceiver Reconfiguration Controller
4.3.1.9. VIP Bypass and Audio, Auxiliary and InfoFrame Buffers
4.3.1.10. Transceiver Native PHY (TX)
4.3.1.11. Transceiver PHY Reset Controller
4.3.1.12. Oversampler (TX)
4.3.1.13. Clock Enable Generator
4.3.1.14. Platform Designer System
5.1. Source Functional Description
5.2. Source Interfaces
5.3. Source Clock Tree
5.4. Link Training Procedure
5.5. FRL Clocking Scheme
5.6. Valid Video Data
5.7. Source Deep Color Implementation When Support FRL = 0
5.8. Source Deep Color Implementation When Support FRL = 1
5.9. Variable Refresh Rate (VRR) and Auto Low Latency Mode (ALLM)
5.1.1. Source Scrambler, TMDS/TERC4 Encoder
5.1.2. Source Video Resampler
5.1.3. Source Window of Opportunity Generator
5.1.4. Source Auxiliary Packet Encoder
5.1.5. Source Auxiliary Packet Generators
5.1.6. Source Auxiliary Data Path Multiplexers
5.1.7. Source Auxiliary Control Port
5.1.8. Source Audio Encoder
5.1.9. HDCP 1.4 TX Architecture
5.1.10. HDCP 2.3 TX Architecture
5.1.11. FRL Packetizer
5.1.12. FRL Character Block and Super Block Mapping
5.1.13. Reed-Solomon (RS) Forward Error Correction (FEC) Generation and Insertion
5.1.14. FRL Scrambler and Encoder
5.1.15. Source FRL Resampler
5.1.16. TX Core-PHY Interface
5.1.17. I2C Master
5.1.18. AXI4-Stream to Clocked Video Converter (AXI2CV)
5.1.19. AXI4-Stream to Clocked Video Converter (AXI2CV) Remap
5.1.20. Avalon Memory-Mapped Demultiplexer
5.1.21. HDMI TX Register
5.1.22. HDMI TX Interrupt
5.1.23. TX AXI4-Stream Auxiliary Bridge
5.1.24. TX Auxiliary User Packet
5.1.25. TX AXI4-Stream Auxiliary Arbiter
5.1.26. TX AXI4-Stream Auxiliary Packetizer
5.1.27. TX Avalon-ST Auxiliary Arbiter
6.1.1. Sink Word Alignment and Channel Deskew
6.1.2. Sink Descrambler, TMDS/TERC4 Decoder
6.1.3. Sink Auxiliary Decoder
6.1.4. Sink Auxiliary Packet Capture
6.1.5. Sink Video Resampler
6.1.6. Sink Auxiliary Data Port
6.1.7. Sink Audio Decoder
6.1.8. Status and Control Data Channel (SCDC) Interface
6.1.9. HDCP 1.4 RX Architecture
6.1.10. HDCP 2.3 RX Architecture
6.1.11. FRL Depacketizer
6.1.12. Sink FRL Character Block and Super Block Demapper
6.1.13. Sink FRL Descrambler and Decoder
6.1.14. Sink FRL Resampler
6.1.15. RX Core-PHY Interface
6.1.16. I2C Slave
6.1.17. I2C and EDID RAM Blocks
6.1.18. Clocked Video to AXI4-Stream (CV2AXI) Remap
6.1.19. Clocked Video to AXI4-Stream Converter (CV2AXI)
6.1.20. Avalon Memory-Mapped Demultiplexer
6.1.21. HDMI RX Register
6.1.22. HDMI RX Interrupt
6.1.23. RX AXI4-Stream Auxiliary Bridge
6.1.24. RX Auxiliary Packet Filter
6.1.25. RX Auxiliary User Packetizer
6.1.26. Variable Refresh Rate(VRR) and Auto Low Latency Mode (ALLM)
9.1.1.1. STATUS_CONTROL (0x00)
9.1.1.2. IRQ_STATUS (0x01)
9.1.1.3. IRQ_MASK (0x02)
9.1.1.4. VIDEO_FORMAT (0x03)
9.1.1.5. AVI_CONTROL (0x08)
9.1.1.6. AVI_PACKET_DATA0 (0x09)
9.1.1.7. AVI_PACKET_DATA0 (0x0A)
9.1.1.8. AVI_PACKET_DATA2 (0x0B)
9.1.1.9. AVI_PACKET_DATA3 (0x0C)
9.1.1.10. VSI_CONTROL (0x0D)
9.1.1.11. VSI_PACKET_HEADER (0x0E)
9.1.1.12. VSI_PACKET_DATA0 (0x0F)
9.1.1.13. VSI_PACKET_DATA1 (0x10)
9.1.1.14. USER_PACKET_STATUS_CONTROL (0x12)
9.1.1.15. USER_PACKET_HEADER (0x013)
9.1.1.16. USER_PACKET_DATA0 (0x014)
9.1.1.17. USER_PACKET_DATA1 (0x015)
9.1.1.18. USER_PACKET_DATA2 (0x016)
9.1.1.19. USER_PACKET_DATA3 (0x017)
9.1.1.20. USER_PACKET_DATA4 (0x018)
9.1.1.21. USER_PACKET_DATA5 (0x019)
9.1.1.22. USER_PACKET_DATA6 (0x01A)
9.1.1.23. USER_PACKET_DATA7 (0x01B)
9.1.1.24. AUDIO_INFOFRAME_CONTROL (0x20)
9.1.1.25. AUDIO_INFOFRAME_PACKET_DATA0 (0x21)
9.1.1.26. AUDIO_INFOFRAME_PACKET_DATA1 (0x22)
9.1.1.27. AUDIO_METADATA_CONTROL (0x24)
9.1.1.28. AUDIO_METADATA_PACKET_HEADER (0x025)
9.1.1.29. AUDIO_METADATA_PACKET_DATA0 (0x026)
9.1.1.30. AUDIO_METADATA_PACKET_DATA1 (0x027)
9.1.1.31. AUDIO_METADATA_PACKET_DATA2 (0x028)
9.1.1.32. AUDIO_METADATA_PACKET_DATA3 (0x029)
9.1.1.33. AUDIO_METADATA_PACKET_DATA4 (0x02A)
9.1.1.34. AUDIO_METADATA_PACKET_DATA5 (0x02B)
9.1.1.35. SCDC_FRL_CONTROL (0x031)
9.2.2.1. STATUS (0x50)
9.2.2.2. VIDEO_MODE_MATCH (0x51)
9.2.2.3. VIDEO_MODE_BANK_SELECT (0x53)
9.2.2.4. VIDEO_MODE_CONTROL (0x54)
9.2.2.5. VIDEO_MODE_SAMPLE_COUNT(0x55)
9.2.2.6. VIDEO_MODE_F0_LINE_COUNT (0x56)
9.2.2.7. VIDEO_MODE_F1_LINE_COUNT (0x57)
9.2.2.8. VIDEO_MODE_HORIZONTAL_FRONT_PORCH (0x58)
9.2.2.9. VIDEO_MODE_HORIZONTAL_SYNC_LENGTH (0x59)
9.2.2.10. VIDEO_MODE_HORIZONTAL_BLANKING (0x5A)
9.2.2.11. VIDEO_MODE_VERTICAL_FRONT_PORCH (0x5B)
9.2.2.12. VIDEO_MODE_VERTICAL_SYNC_LENGTH (0x5C)
9.2.2.13. VIDEO_MODE_VERTICAL_BLANKING (0x5D)
9.2.2.14. VIDEO_MODE_F0_VERTICAL_FRONT_PORCH (0x5E)
9.2.2.15. VIDEO_MODE_F0_VERTICAL_SYNC_LENGTH (0x5F)
9.2.2.16. VIDEO_MODE_F0_VERTICAL_BLANKING (0x60)
9.2.2.17. VIDEO_MODE_ACTIVE_PICTURE_LINE (0x61)
9.2.2.18. VIDEO_MODE_F0_VERTICAL_RISING (0x62)
9.2.2.19. VIDEO_MODE_FIELD_RISING (0x63)
9.2.2.20. VIDEO_MODE_FIELD_FALLING (0x64)
9.2.2.21. VIDEO_MODE_VALID (0x6D)
9.3.1.1. STATUS (0x01)
9.3.1.2. IRQ_STATUS (0x02)
9.3.1.3. IRQ_MASK (0x03)
9.3.1.4. HOTPLUG (0x04)
9.3.1.5. LINK_MODE (0x05)
9.3.1.6. VIDEO_COLOUR (0x06)
9.3.1.7. AVI_PACKET_DATA0 (0x0C)
9.3.1.8. AVI_PACKET_DATA1 (0x0D)
9.3.1.9. AVI_PACKET_DATA2 (0x0E)
9.3.1.10. AVI_PACKET_DATA3 (0x0F)
9.3.1.11. USER_PACKET_FILTER (0x10)
9.3.1.12. USER_BUFFER_STATUS_CONTROL (0x11)
9.3.1.13. USER_BUFFER_LEVEL (0x12)
9.3.1.14. USER_BUFFER_DATA (0x13)
9.3.1.15. AUX_PACKET_FILTER (0x14)
9.3.1.16. AUDIO_INFOFRAME_PACKET_DATA0 (0x21)
9.3.1.17. AUDIO_INFOFRAME _PACKET_DATA1 (0x22)
9.3.1.18. AUDIO_METADATA _PACKET_HEADER (0x25)
9.3.1.19. AUDIO_METADATA _PACKET_DATA0 (0x26)
9.3.1.20. AUDIO_METADATA _PACKET_DATA1 (0x27)
9.3.1.21. AUDIO_METADATA _PACKET_DATA2 (0x28)
9.3.1.22. AUDIO_METADATA _PACKET_DATA3 (0x29)
9.3.1.23. AUDIO_METADATA _PACKET_DATA4 (0x2A)
9.3.1.24. AUDIO_METADATA _PACKET_DATA5 (0x2B)
9.3.1.25. VSI_PACKET_DATA0 (0x2C)
9.3.1.26. VSI_PACKET_DATA1 (0x2D)
9.3.1.27. SCDC_FRL_STATUS (0x2E)
9.3.1.28. SCDC_FRL_CONTROL (0x2F)
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Ixiasoft
2.4. Resource Utilization
The resource utilization data indicates typical expected performance for the HDMI Intel® FPGA IP in the Intel® Quartus® Prime Pro Edition software.
Devices | Maximum Data Rate (Mbps) | |
---|---|---|
2 Pixels per Clock (Support FRL = 0) |
8 Pixels per Clock (Support FRL = 1) |
|
Intel® Stratix® 10 | 5,940 (Example: 4Kp60 8 bpc) |
12,000 (Example: 8Kp30 12 bpc) |
Intel® Arria® 10 | 5,940 (Example: 4Kp60 8 bpc) |
12,000 (Example: 8Kp30 12 bpc) |
Intel® Cyclone® 10 GX | 5,940 (Example: 4Kp60 8 bpc) |
Not Supported |
Intel® Agilex™ F-tile | Not supported | 12,000 (Example: 8Kp30 12 bpc) |
Device | Pixels per Clock | Direction | ALMs | Logic Registers | Memory | ||
---|---|---|---|---|---|---|---|
Primary | Secondary | Bits | M10K or M20K | ||||
Intel® Stratix® 10 H-tile (Support FRL = 0) 1 |
2 | RX | 5.041 | 6,633 | 902 | 38,400 | 14 |
2 | TX | 4,975 | 7,559 | 1,368 | 37,568 | 13 | |
Intel® Stratix® 10 L-tile (Support FRL = 0) 1 |
2 | RX | 5,025 | 6,584 | 967 | 38,400 | 14 |
2 | TX | 4,966 | 7,539 | 1,425 | 37,568 | 13 | |
Intel® Arria® 10 (Support FRL = 0) |
2 | RX | 3,768 | 5,716 | 1,049 | 36,352 | 14 |
2 | TX | 4,445 | 7,016 | 1,701 | 36,968 | 13 | |
Intel® Arria® 10 (Support FRL = 1)2 |
8 | RX | 48,865 | 55,417 | 13,067 | 376,832 | 87 |
8 | TX | 30,092 | 35,533 | 6,839 | 276,288 | 60 | |
Intel® Cyclone® 10 GX | 2 | RX | 4,000 | 5,768 | 965 | 38,400 | 14 |
2 | TX | 4,484 | 7,167 | 1,629 | 36,968 | 13 | |
Intel® Agilex™ F-tile (Support FRL = 1)1 | 8 | RX | 33,845 | 3,942 | 8,517 | 229,888 | 62 |
8 | TX | 23,217 | 28,174 | 5,590 | 213,376 | 36 |
Device | Lane Rate (Mbps) | Transceiver Interface Width (bits) | Speed Grade |
---|---|---|---|
Intel® Stratix® 10 | 12,000 | 40 | -1, -2 3 |
Intel® Arria® 10 | 12,000 | 40 | -1, -2 |
Intel® Agilex™ F-tile | 12,000 | 40 | -1 |
Device | Lane Rate (Mbps) | Interface Width (bits) | Speed Grades |
---|---|---|---|
Intel® Stratix® 10 | 6,000 | 20 | -1, -2 |
Intel® Arria® 10 | 6,000 | 20 | -1, -2 |
Intel® Cyclone® 10 GX | 6,000 | 20 | -5 |
Device | HDCP IP | Support HDCP Key Management | Support FRL | Pixels/TMDS Symbols Per Clock | ALMs | Combinational ALUTs | Registers | M20K | DSP |
---|---|---|---|---|---|---|---|---|---|
Intel® Arria® 10 | HDCP 2.3 TX | 0 | 0 | 2 | 6,479 | 10,548 | 12,015 | 10 | 3 |
1 | 8 | 16,629 | 28,783 | 23,606 | 10 | 3 | |||
1 | 0 | 2 | 6,875 | 11,338 | 12,793 | 12 | 3 | ||
1 | 8 | 17,048 | 29,534 | 24,367 | 12 | 3 | |||
HDCP 2.3 RX | 0 | 0 | 2 | 7,119 | 11,685 | 12,673 | 11 | 3 | |
1 | 8 | 17,083 | 30,148 | 24,068 | 11 | 3 | |||
1 | 0 | 2 | 7,543 | 12,420 | 13,406 | 13 | 3 | ||
1 | 8 | 17,552 | 30,861 | 24,806 | 13 | 3 | |||
HDCP 1.4 TX | 0 | 0, 1 | 2 | 1,665 | 2,626 | 4,411 | 2 | 0 | |
1 | 0, 1 | 2 | 2,142 | 3,411 | 5,167 | 4 | 0 | ||
HDCP 1.4 RX | 0 | 0, 1 | 2 | 1,170 | 1,850 | 3,407 | 3 | 0 | |
1 | 0, 1 | 2 | 1,616 | 2,558 | 4,207 | 5 | 0 | ||
Intel® Stratix® 10 | HDCP 2.3 TX | 0 | 0 | 2 | 7,213 | 11,582 | 12,810 | 10 | 3 |
1 | 8 | 17,755 | 29,784 | 24,428 | 10 | 3 | |||
1 | 0 | 2 | 7,888 | 12,473 | 13,188 | 12 | 3 | ||
1 | 8 | 18,477 | 30,540 | 25,191 | 12 | 3 | |||
HDCP 2.3 RX | 0 | 0 | 2 | 8,145 | 12,691 | 13,438 | 11 | 3 | |
1 | 8 | 18,482 | 30,881 | 25,422 | 11 | 3 | |||
1 | 0 | 2 | 8,644 | 13,382 | 13,640 | 13 | 3 | ||
1 | 8 | 19,096 | 31,460 | 26,138 | 13 | 3 | |||
HDCP 1.4 TX | 0 | 0, 1 | 2 | 2,320 | 2,937 | 4,544 | 2 | 0 | |
1 | 0, 1 | 2 | 2,881 | 3,797 | 5,170 | 4 | 0 | ||
HDCP 1.4 RX | 0 | 0, 1 | 2 | 1,784 | 2,135 | 3,605 | 3 | 0 | |
1 | 0, 1 | 2 | 2,293 | 2,897 | 4,219 | 5 | 0 |
1 Resource data for Support FRL = 1 design is not finalized.
2 Contact Intel Sales for further optimization for specific device variants.
3 Contact Intel Sales if you need to use -2 speed grade.