HDMI Intel® FPGA IP User Guide

ID 683798
Date 4/22/2022
Public

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5.1.24. TX Auxiliary User Packet

The user defined packet interface provides a means for the host processor to load an array of predefined HDMI data packets into a buffer to be outputted into the HDMI stream. Refer to the USER_PACKET_* in HDMI Source Register for the details on the user packet register configuration.

The packet output is triggered by the active edge of the vertical sync pulse. The interface can operate in a repeated mode where the packets are sent every frame, or in a ‘one-shot’ mode where the contents are zeroed immediately after being sent. This is controlled by the pckt_mode register.

The contents of each slot in the data packet array are sent once each frame. If the slot is all zeros, then a ‘null’ packet as defined by the HDMI 2.0 specification is sent.

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