HDMI Intel® FPGA IP User Guide

ID 683798
Date 4/22/2022
Public

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5.7. Source Deep Color Implementation When Support FRL = 0

When Support FRL = 0, you need to provide the ls_clk and vid_clk clocks according to the color depth ratio. The HDMI TX core carries 24, 30, 36 or 48 bits per pixel (bpp).

ls_clk frequency = data rate per lane / effective transceiver width = data rate per lane / 20

Note: The effective transceiver width in TMDS mode is also 20.

vid_clk frequency = (data rate per lane / effective transceiver width) / color depth ratio

Table 42.  Color Depth Ratio for Bits per Color
Bits per Color Color Depth Ratio
8 1.6
10 1.25
12 1.5
16 2.0
Figure 40. Deep Color Implementation When Support FRL = 0
Figure 41. 10 Bits per Component (30 Bits per Pixel)When operating in 10 bits per component, the vid_clk frequency to ls_clk frequency ratio is 4:5. For every 5 ls_clk cycles, there should be 4 vid_clk cycles.
Figure 42. 12 Bits per Component (36 Bits per Pixel)When operating in 12 bits per component, the vid_clk frequency to ls_clk frequency ratio is 2:3. For every 3 ls_clk cycles, there should be 2 vid_clk cycles.
Figure 43. 16 Bits per Component (48 Bits per Pixel)When operating in 16 bits per component, the vid_clk frequency to ls_clk frequency ratio is 1:2. For every 1 ls_clk cycle, there should be 2 vid_clk cycles.

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