HDMI Intel® FPGA IP User Guide

ID 683798
Date 4/22/2022
Public

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Document Table of Contents

4.3.1. HDMI Hardware Design Components

The demonstration designs instantiate the Video and Image Processing (VIP) Suite IP cores or FIFO buffers to perform a direct HDMI video stream passthrough between the HDMI sink and source.

The hardware demonstration design comprises the following components:

  • HDMI sink
    • Transceiver Native PHY (RX)
    • Transceiver PHY Reset Controller (RX)
    • PLL
    • PLL Reconfiguration
    • Multirate Reconfiguration Controller (RX)
    • Oversampler (RX)
    • DCFIFO
  • Sink Display Data Channel (DDC) and Status and Control Data Channel (SCDC)
  • Transceiver Reconfiguration Controller
  • VIP bypass and Audio, Auxiliary and InfoFrame buffers
  • Platform Designer system
    • VIP passthrough for HDMI video stream
    • Source SCDC controller
    • HDMI source reconfiguration controller
  • HDMI source
    • Transceiver Native PHY (TX)
    • Transceiver fPLL
    • Transceiver PHY Reset Controller (TX)
    • PLL
    • PLL Reconfiguration
    • Oversampler (TX)
    • DCFIFO
    • Clock Enable Generator
Figure 10. HDMI Hardware Design Example Block DiagramThe figure below shows a high level architecture of the design.

The following details of the design example architecture correspond to the numbers in the block diagram.

  1. The sink TMDS data has three channels: data channel 0 (blue), data channel 1 (green), and data channel 2 (red).
  2. The Oversampler (RX) and dual-clock FIFO (DCFIFO) instances are duplicated for each TMDS data channel (0,1,2).
  3. The video data input width for each color channel of the HDMI RX core is equivalent to RX transceiver PCS-PLD parallel data width per channel.
  4. Each color channel is fixed at 16 bpc. The video data output width of the HDMI RX core is equivalent to the value of symbols per clock*16*3.
  5. The video data input width of the Clocked Video Input (CVI) and Clocked Video Output (CVO) IP cores are equivalent to the value of NUMBER_OF_PIXELS_IN_PARALLEL * BITS_PER_PIXEL_PER_COLOR_PLANE * NUMBER_OF_COLOR_PLANES. To interface with the HDMI core, the values of NUMBER_OF_PIXELS_IN_PARALLEL, BITS_PER_PIXEL_PER_COLOR_PLANE, and NUMBER_OF_COLOR_PLANES must match the symbols per clock, 16 and 3 respectively.
  6. The video data input width of the HDMI TX core is equivalent to the value of symbols per clock*16*3. You can use the user switch to select the video data from the CVO IP core (VIP passthrough) or DCFIFO (VIP bypass).
  7. The video data output width for each color channel of the HDMI TX core is equivalent to TX transceiver PCS-PLD parallel data width per channel.
  8. The DCFIFO and the Oversampler (TX) instances are duplicated for each TMDS data channel (0,1,2) and clock channel.
  9. The Oversampler (TX) uses the clock enable signal to read data from the DCFIFO.
  10. The source TMDS data has four channels: data channel 0 (blue), data channel 1 (green), data channel 2 (red), and clock channel.
  11. The RX Multirate Reconfiguration Controller requires the status of TMDS_Bit_clock_Ratio port to perform appropriate RX reconfiguration between the TMDS character rates below 340 Mcsc (HDMI 1.4b) and above 340 Mcsc (HDMI 2.0b). The status of the port is also required by the Nios II processor and the HDMI TX core to perform appropriate TX reconfiguration and scrambling.
  12. The reset control and lock status signals from HDMI PLL, RX Transceiver Reset Controller and HDMI RX core.
  13. The reset and oversampling control signals for HDMI PLL, TX Transceiver Reset Controller, and HDMI TX core. The lock status and rate detection measure valid signals from the HDMI sink initiate the TX reconfiguration process.
  14. The I2C SCL and SDA lines with tristate buffer for bidirectional configuration. Use the ALTIOBUF IP core for Arria V and Stratix V devices.
  15. The SCDC is mainly designed for the source to update the TMDS_Bit_Clock_Ratio and Scrambler_Enable bits of the sink TMDS Configuration register. .

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