HDMI Intel® FPGA IP User Guide

ID 683798
Date 4/22/2022
Public

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5.1.1. Source Scrambler, TMDS/TERC4 Encoder

The TMDS/TERC4 encoder implements 8-bit to 10-bit and 4-bit to 10-bit algorithms as defined in the HDMI 1.4b Specification Section 5.4. Each data channel, with exception of the clock channel, has its own encoder. You can configure the core to enable scrambling, as defined in the HDMI 2.0b Specification Section 6.1.2, before TMDS/TERC4 encoding.

The encoder processes symbol data at 1, 2, or 4 symbols per clock. When the encoder operates in 2 or 4 symbols per clock, it also produces the output in the form of two or four encoded symbols per clock.

The TMDS/TERC4 encoder also produces digital visual interface (DVI) signaling when you deassert the mode input signal. DVI signaling is identical to HDMI signaling, except for the absence of data and video islands and TERC4 auxiliary data.

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