5.2.4. Functional Simulation with VHDL
Only the top-level IP instance file is guaranteed to be written in VHDL; submodules can be deployed as Verilog/SystemVerilog (encrypted or plain text) files, or VHDL files. Note that the QuestaSim - Intel FPGA Edition is not restricted to a single HDL language, however, some files may be encrypted in order to be excluded from the maximum unencrypted module limit of this tool.
Because the VHDL fileset consists of both VHDL and Verilog files, you must follow certain mixed-language simulation guidelines. The general guideline for mixed-language simulation is that you must always link the Verilog files (whether encrypted or not) against the Verilog version of the libraries, and the VHDL files (whether SimGen-generated or pure VHDL) against the VHDL libraries.
Simulation scripts for the Cadence, Siemens EDA, and Synopsys* simulators are provided for you to run the design example. Simulation scripts in the simulation folders are located as follows:
For more information about simulating Verilog HDL or VHDL designs using command lines, refer to the Questa - Intel FPGA Edition, ModelSim, and QuestaSim Simulator Support chapter in the Intel® Quartus® Prime Pro Edition User Guide, Third-party Simulation.
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