External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 3/28/2022

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Document Table of Contents QDR IV SRAM Commands and Addresses, AP, and AINV Signals

The CK and CK# signals clock the commands and addresses into the memory devices. There is one pair of CK and CK# pins per QDR IV SRAM device. These pins operate at double data rate using both rising and falling edge. The rising edge of CK latches the addresses for port A, while the falling edge of CK latches the addresses inputs for port B.

QDR IV SRAM devices have the ability to invert all address pins to reduce potential simultaneous switching noise. Such inversion is accomplished using the Address Inversion Pin for Address and Address Parity Inputs (AINV), which assumes an address parity of 0, and indicates whether the address bus and address parity are inverted.

The above features are available as Option Control parameters in the Configuration Register Settings section of the Memory tab in the parameter editor. The commands and addresses must meet the memory address and command setup (tAS, tCS) and hold (tAH, tCH) time requirements.

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