184.108.40.206. ISSPs Tab
To reread the probe data from the ISSPs in the design, expand the In-System Probes section and click the Update Probe Info button.
To reread the source data from the ISSPs in the design, expand the In-System Sources section and click the Update Source Info button.
To overwrite the source data, select the Instance Name and change the Writedata value. The new source value is written when you click Write Source Info.
Descriptions of ISSPs in the EMIF Design Example
|PLLL||PLL Lock signal. A value of 1 means that the PLL is locked, a value of 0 means that the PLL cannot lock to the reference clock.|
|RCNT||Total read data count.|
|FCNT||Total fail count (data mismatch count).|
|FADR||First address where a data mismatch is reported.|
|RAVP||Read data valid from the data before the first failing address.|
|RAVN||Read data valid from the data after the first failing address.|
|PNF#||Persistent Pass Not Fail Flag. A 1 indicates pass, 0 indicates fail.|
|FPN#||PNF flag for the first data mismatch.|
|FEX#||The expected read data for the first failing read.|
|FEP#||The expected read data before the first failing read.|
|FEN#||The expected read data after the first failing read.|
|ACT#||The actual read data for the first failing read.|
|ACP#||The actual read data before the first failing read.|
|ACN#||The actual read data after the first failing read.|
|LRD#||The repeated read result. When there is an error, the driver reads again from the first failing address. This is the PNF flag for the repeated read.|
|AVSC||Avalon Stall Count - a concatenation of the following three 32-bit signals (MSB to LSB):
|PALP||Clock phase alignment lock status.|
|PALS||Clock phase alignment lock (secondary).
Note: This is not used in Agilex FPGAs.
|CALC||Calibration counter. Highest bit is a done signal — a value of 1 means that calibration has completed, and a value of 0 means that calibration is still in progress. The other 32 bits are a clock counter which tracks the number of clocks passed during calibration.|
|TGP||Traffic Generator Pass Flag. Pass=1.|
|TGF||Traffic Generator Fail Flag. Fail=1.|
|TGT||Traffic Generator Timeout. Timeout=1.|
|TGR||Traffic Generator Reset. Active High. Toggle TGR to rerun the traffic generator.|
|RSTN||Global Reset for the design example. Active Low. Toggle RSTN to reset and recalibrate the interface.|
|WORM||Set to 1 to enable WORM mode. In WORM mode, if a data mismatch is encountered, the system stops as much of the traffic as possible and issues a read to the same address. In this mode, the persistent PNF is no longer meaningful as execution stops at the first data mismatch. By default, WORM mode is turned off.|
|PRTY||Indicates DDR4 memory parity status. A value of 0 indicates no error, and a value of 1 indicates an error. The value is not updated if the design is not DDR4, or if the AC Parity Latency parameter is disabled in the parameter editor.|
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