External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 3/28/2022

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Document Table of Contents Skew Matching Guidelines for QDR-IV Configurations

The guidelines in this topic apply to QDR-IV memory configurations.

Board designers must observe the following guidelines for QDR-IV skew matching:

  • Perform skew matching in time (picoseconds) rather than in actual trace length, to better account for via delays when signals are routed on different layers.
  • Include both package per-pin skew and PCB delay when performing skew matching.
  • Skew (length) matching for the alert signal is not required.

The following table provides skew matching guidelines for QDR-IV topologies.

Table 149.  QDR-IV Skew Matching Guidelines
QDR-IV Length Matching Rules Length Matching in Time (ps)
Length Matching between DK/QK and CLK -50 < CLK - DK/QK < 50ps
Length Matching between DQ and DK/QK within byte -5ps < DQ - DK/QK < 5ps
Length matching between DK/QK and DK/QK# < 1 ps
Length matching between DK and QK pairs < 5 ps
Length matching between CLK and CLK# < 1 ps
Length Matching between CMD and CTRL and Clock -20 ps < CLK - CMD < 20 ps
Length matching among CMD and CTRL within each channel < 20 ps
Include package length in skew matching for FPGA device with no migration Required
Include package length in skew matching for FPGA device with migration. Not recommended

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