External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 3/28/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents Memory Configuration Tab

The Memory Configuration tab shows the IP settings, which were defined when you parameterized the EMIF IP.

Figure 147. Memory Configuration Tab

Did you find the information on this page useful?

Characters remaining:

Feedback Message