External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 3/28/2022
Public

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11.4. Verifying Memory IP Using the Signal Tap Logic Analyzer

The Signal Tap logic analyzer shows read and write activity in the system.

For more information about using the Signal Tap logic analyzer, refer to the Intel® Quartus® Prime Pro Edition User Guide: Debug Tools.

To add the Signal Tap logic analyzer, follow these steps:

  1. On the Tools menu click Signal Tap Logic Analyzer .
  2. In the Signal Configuration window next to the Clock box, click (Browse Node Finder).
  3. Type the memory interface system clock (typically * emif_usr_clk) in the Named box, for Filter select Signal Tap: presynthesis and click List.
  4. Select the memory interface clock that is exposed to the user logic.
  5. Click OK.
  6. Under Signal Configuration, specify the following settings:
    • For Sample depth, select 512
    • For RAM type, select Auto
    • For Trigger flow control, select Sequential
    • For Trigger position, select Center trigger position
    • For Trigger conditions , select 1

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