External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 3/28/2022

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6.5.3. General Layout Routing Guidelines

Follow the guidelines in this section for routing from the FPGA to memory for Intel® Agilex™ devices.

For maximum channel margin, you should consider the following general routing optimizations during the layout design phase:

  • When routing the memory interface, ensure that there are solid ground reference planes without any plane splits or voids, to ensure an uninterrupted current return path.
  • For signal vias in layer transitions, you must place ground stitching vias close by, within 80 mil in distance (closer is better), and in between signal vias, to minimize crosstalk among signal vias. Avoid any unnecessary signal layer transitions to minimize crosstalk, loss, and skews.
  • Trace impedance plays an important role in signal integrity; board designers must follow impedance recommendations for each signal group and configuration according to the guidelines in this document. If you use a different stackup than the reference stackup in the PCB design, you must tune the trace width and geometries to achieve the impedance recommendations.
  • Intel® recommends using 45-degree angles (not sharp 90-degree corners) when routing signal turns. Use 3×h spacing for serpentine routing, where h is the height or distance from the trace to the nearest GND reference plane.
  • Avoid referencing a signal to both power and ground planes at the same time (dual referencing), for signal return paths. When this cannot be avoided, ensure that the closer reference plane is solid ground, and the far side power plane is not noisy.
  • Avoid routing two internal signal layers adjacent to each other (dual stripline routing). When this cannot be avoided, use angled routing between two signal layers to minimize crosstalk and coupling between the layers.
  • Follow time-domain length and skew matching rules to ensure that your interface meets timing requirements. You should route signals from the same byte or group together on the same layer to avoid any out-of-phase crosstalk caused by varying layer transition lengths.
  • To optimize memory interface margins, Intel® recommends the following routing strategies:
    • For DIMM configurations, route DQ and DQS signals on shallow layers with short via transition lengths, because they have tighter timing margins than address, command, and control signals. (Shallow layers are those above the PCB core where via transition lengths are short.)
    • For discrete device configurations, route address, command, and control signals on shallow layers.
  • For boards thicker than 65 mil, Intel® recommends alternating adjacent FPGA EMIF BGA/ball rows with deep and shallow board via transitions to minimize crosstalk between adjacent bytes. This method is illustrated in the following figure:
    Figure 92. Recommended alternate adjacent via transitions to avoid crosstalk between adjacent bytes
  • For boards thicker than 65 mil, using the pin-through-hole (PTH) type of DIMM connector, Intel® recommends implementing a loop-routing-around-DIMM-pin structure (Lcomp) to improve impedance matching between signal routing and the DIMM connector. Refer to the following figure.
    Figure 93. Recommended Lcomp structure for better impedance matching
  • For PCB designs using a surface mount technology (SMT) type of DIMM connector, Intel® recommends placing a cutout (void) in the ground reference plane underneath the connector pads for DDR4 signals to minimize connector pad capacitance. Refer to the following figure for the recommended cutout on ground reference plane underneath the connector pad on surface layer.
Figure 94. Recommended Cutout on Ground Reference Plane
Figure 95. Closeup View of Connections
Figure 96. Closeup View of Connections
  • For two-DIMMs-per-channel (2DPC) in UDIMM, RDIMM, or LRDIMM configurations with an SMT type of DIMM connector, Intel® recommends have signal transition via to the near DIMM connector, then routing the trace on the surface layer (microstrip line routing) through connector pads to the far DIMM connector. The following figure depicts the recommended routing guidelines between two DIMMs in one channel.
    Figure 97. Recommended routing guidelines between two DIMMs in 2DPC EMIF topology

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