External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 3/28/2022
Public

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11.10. EMIF On-Chip Debug Port

The On-Chip Debug Port (cal_debug) provides access to the I/O SSM user-ram and calbus bridge, which contain debug information collected during EMIF calibration, and tools that can help analyze or improve interface stability.

The cal_debug is an Avalon® memory-mapped interface. This port does not provide access outside of the address ranges of the user-ram and calbus bridge.

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