External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 3/28/2022
Public

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6.5.6.3. ADDR/CMD Reference Voltage/RESET Signal Routing Guidelines for Single Rank x 8 and R Rank x 16 Discrete (Component) Topologies

The target impedance for the RESET signal is 50 ohms. The RESET signal must have at least 3 × h (where h is the distance from the trace to the nearest reference plane) spacing to other nearby signals on the same layer. The end-to-end RESET trace length is not limited but must not exceed 5 inches to the first DRAM.

The following figure shows the RESET routing scheme, which you can apply to both single rank x 8 and single rank x16 topologies.

Figure 110. RESET Scheme for Single Rank x8 and Single Rank x16 Topologies

The Address/Command reference voltage input (VREF_CA) must track the VTT regulator output as closely as possible. There are two methods to achieve this:

One method is to use a regulator that provides a dedicated tracking voltage reference output that can be connected directly to memory component VREF_CA inputs, as shown in the figure below.

Figure 112. VTT Regulator Supplies VREF_CA Output

A second method is to create a voltage divider using precision resistors. Place the resistor network in a location that is likely to track IR losses on the VDD supply due to memory loading (that is, close to the VTT regulator or memory components, rather than next to the VDD regulator output). The following figure illustrates this configuration.

Figure 113. Resistor Divider Provides the VREF_CA Signal

Intel® recommends using a PCB trace width of at least 10 mils for VREF_CA routing. The VREF_CA signal must have at least 3×h spacing (where h is the distance or height from the trace to the nearest reference plane) to other nearby signals on the same layer.

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