External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 3/28/2022
Public

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11.7.4.3. Guidelines for Debugging Calibration Issues

The following topics provide general guidelines for debugging calibration-related issues.

General Hardware Debugging for Calibration Issues

  1. Verify that the correct memory component or DIMM is installed on the circuit board.
  2. Begin with the design example generated by the Intel® Quartus® Prime software as a starting point to debug your issue. Review and update the memory timing parameter, CAS, and Write CAS latency based on the speed bin of the targeted memory component and the operating frequency of your interface. Incorrect memory timing parameter, CAS, or Write CAS latency can cause data corruption in the memory component.
  3. Verify that the design has the correct pin locations and I/O standard. Although the Fitter may place some unassigned pins automatically, you should provide the pin location assignments and I/O standard for all the EMIF pins in your design. Check the Fitter report to ensure that all the pins are placed correctly in the design.
  4. Ensure that the PCB has correct termination resistors on the address and command signals. Refer to the Board Layout Guidelines section of this user guide for more information on suggested termination values.
  5. Each EMIF instance has its own RZQ pin. Ensure that every RZQ pin on the FPGA side is connected to GND through a 240 ohm, 1% resistor.
  6. If you are using discrete memory components, ensure that every ZQ pin on the memory component side is connected to GND through a 240 ohm, 1 % resistor.
  7. Ensure that the EMIF IP is instantiated with the correct I/O PLL reference clock frequency and I/O standard. The reference clock must be stable and running at the expected frequency during calibration, after calibration, and during user mode. Probe the memory clock frequency to confirm that the memory clock is toggling at the expected frequency after configuring the device.
  8. Check the relevant voltage rails for absolute value and for worst case noise. Suggested rails are VCC,VCCP, VCCIO_PIO, VCCPT,VCCA_PLL, VREF, VTT and the power supplies at the DDR4 memory device.
  9. Ensure that the reset signal to the DDR4 IP is driven correctly. The reset request is sent by transitioning the local_reset_req signal from low to high, then keeping the signal at the high state for a minimum of 2 EMIF core clock cycles, then transitioning the signal from high to low.
  10. Check to determine whether the calibration problem exists on more than one board.
  11. Determine whether the issue exists at lower interface frequencies. If the board passes at lower frequencies, evaluate the I/O Timing to ensure that the PCB and associated system is capable of running at your targeted frequency. Refer to Intel® Agilex™ FPGA EMIF IP – I/O Timing Closure for more information.
  12. Repeat the calibration multiple times without reconfiguring the device, to see whether the calibration can recover by recalibrating the interface.
  13. Rerun the calibration by reconfiguring the device to see whether the calibration can recover after reconfiguring the device.

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