6.5.5. Intel® Agilex™ EMIF-Specific Routing Guidelines for Various DDR4 Topologies
The Intel® Agilex™ family pin floorplan is a HEX pattern with 1mm pitch. The following figure shows an example of DDR routing for an IO12 (one-byte data) on PCB within FPGA fan-out region.
The following general notes apply to the EMIF routing guidelines tables in subsequent topics:
- All spacing requirements are the minimum requirement to be met on PCB in EMIF routing guideline table.
- Breakout (BO1/BO2) spacings have two different values in guideline tables. The first value represents minimum spacing between two signals routed as a pair (tightly coupled signals); this value is marked as A (5 mil) in the above figure. The second value represents minimum spacing between two pairs, and is marked as B (17 mil) in the above figure.
- Main route (M) spacings have both value in mil and formula. In formula, h represents the trace-to-nearest-reference-plane height or distance. In cases using a stackup different than the reference stackup, board designers shall use formula to calculate the correct spacing requirements.
- There is no differential impedance target for CLK nor DQS. Board designers shall follow single-ended impedance target and keep the signals within the pair closely coupled, within 3-4 mil spacing. For information on DQS/DQSB and CLK/CLKB, refer to the Skew Matching Guidelines for DDR4 DIMM Topologies and Skew Matching Guidelines for DDR4 Discrete Topologies tables, for DIMM and discrete device implementations, respectively.
- In guideline tables, SL stands for stripline routing recommendation and US stands for upper surface (Microstrip) routing recommendation.
- The trace width value/geometry in guideline tables stands for trace designed for target impedance based on the reference stackup. This trace geometry shall be designed based on actual stackup and target impedance in guideline table.
- In guideline tables, BO1 and BO2 represent fan-out routing lengths. M stands for out of fan-out (PCB main) routing lengths
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