External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 3/28/2022
Public

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9.4. File Organization

This topic lists the SPICE simulation files supplied with the EMIF IP.

The top-level parameterization file accompanies the IP as derived from the settings of that IP instance. The remaining files are common to all IP instances and come as a .ZIP file in the synthesis file set with a name that is unique to the IP.

In the Intel® Quartus® Prime software version 20.3 and later, the top-level SPICE parameterization file has the following location and structure:

altera_emif_arch_fm_<ip_version>/synth/<instance_name>_altera_emif_arch_fm_<ip_version>_<uniquification_code>_ip_parameter.dat

You can find the .ZIP file containing the simulation collateral in the same directory:

altera_emif_arch_fm_<ip_version>/synth/<instance_name>_altera_emif_arch_fm_<ip_version>_<uniquification_code>_spice_files.zip

Table 150.  SPICE Deck File Organization
File Name Function
User-Editable Collateral
membsi_ip_parameters.dat Include file for IP Parameters. You should copy into this file the contents of the IP-specific parameter file that the IP generates.
pin_parasitics.dat Include file containing FPGA and memory package pin parasitic information. You should modify the contents of this file.
finesim_options.inc Include file to specify SPICE simulator options.
Top-Level Simulation Decks
ac_top.sp Top-level SPICE deck for Address/Command simulations.

dq_wr_top.sp

dq_2rank_wr_top.sp

dq_4rank_wr_top.sp

Top-level SPICE deck for FPGA write operations. Use only the file corresponding to the number of DQ ranks in your IP.

dq_rd_top.sp

dq_2rank_rd_top.sp

dq_4rank_rd_top.sp

Top-level SPICE deck for FPGA read operations. Use only the file corresponding to the number of DQ ranks in your IP.
Extracted Models
ac_pcb_wrapper.sp 12-line extraction model for the address/command channel (Lane 0 of the memory interface).
dq_pcb_wrapper.sp 12-line extraction model for the data channel (worst-case DQS group).
ac_mr_conn_wrapper.sp Extraction model for the multi-rank bifurcation point and/or DIMM connector of the address/command channel.
dq_mr_conn_wrapper.sp Extraction model for the multi-rank bifurcation point and/or DIMM connector of the data channel.
ac_dimm_flyby_wrapper.sp Extraction model for the fly-by channel of a component interface, including VTT termination resistors, or the extraction model of the DIMM raw card including VTT termination resistors.
dq_dimm_pkg_wrapper.sp Currently unused.
Buffer Model Wrappers
tx_buffer.sp Wrapper for transmit buffer IBIS models and data generator.
rx_buffer.sp Wrapper for receive buffer IBIS model.
lane_tx12.sp 12-line bundle wrapper for transmit buffers.
lane_rx12.sp 12-line bundle wrapper for receive buffers.
Pattern Generators
dqs_wave.sp Free-running clock pattern generator.
prbs_15.sp PRBS-15 pattern generator. Produces 32,768 pseudo-random bits.
prbs_10_x3.sp PRBS-10 pattern generator. Produces three complete cycles of 1024 pseudo-random bits each for a total of 3,072 bits.

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