External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 3/28/2022
Public

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6.4.1.2. DIMM Options

Unbuffered DIMMs (UDIMMs) require one set of chip-select (CS#), on-die termination (ODT), clock-enable (CKE), and clock pair (CK/CKn) for every physical rank on the DIMM. Many registered DIMMs use only one pair of clocks; however, this is not a universal rule, so you should check your memory vendor's data sheet to be sure. DDR4 registered DIMMs require a minimum of one chip-select signal.
Table 103.  UDIMM, RDIMM, and LRDIMM Pin Options for DDR4
Pins UDIMM Pins (Single Rank) UDIMM Pins (Dual Rank) RDIMM Pins (Single Rank) RDIMM Pins (Dual Rank) LRDIMM Pins (Dual Rank) LRDIMM Pins (Quad Rank)
Data

72 bit DQ[71:0]=

{CB[7:0],

DQ[63:0]}

72 bit DQ[71:0]=

{CB[7:0],

DQ[63:0]}

72 bit DQ[71:0]=

{CB[7:0],

DQ[63:0]}

72 bit DQ[71:0]=

{CB[7:0],

DQ[63:0]}

72 bit DQ[71:0]=

{CB[7:0],

DQ[63:0]}

72 bit DQ[71:0]=

{CB[7:0],

DQ[63:0]}

Data Mask DM#/DBI#[8:0] (1) DM#/DBI#[8:0] (1) DM#/DBI#[8:0] (1) DM#/DBI#[8:0] (1)
Data Strobe x8: DQS[8:0] and DQS#[8:0] x8: DQS[8:0] and DQS#[8:0] x8: DQS[8:0] and DQS#[8:0] x4: DQS[17:0] and DQS#[17:0] x8: DQS[8:0] and DQS#[8:0] x4: DQS[17:0] and DQS#[17:0] x4: DQS[17:0] and DQS#[17:0] x4: DQS[17:0] and DQS#[17:0]
Address

BA[1:0], BG[1:0], A[16:0] -

4GB: A[14:0]

8GB: A[15:0]

16GB: A[16:0] (2)

BA[1:0], BG[1:0], A[16:0] -

8GB: A[14:0]

16GB: A[15:0]

32GB: A[16:0] (2)

BA[1:0], BG[1:0], x8: A[16:0] -

4GB: A[14:0]

8GB: A[15:0]

16GB: A[16:0] (2)

32GB: A[17:0] (3)

BA[1:0], BG[1:0],x8: A[16:0] x4: A[17:0] -

8GB: A[14:0]

16GB: A[15:0]

32GB: A[16:0] (2)

64GB: A[17:0] (3)

BA[1:0], BG[1:0], A[17:0] -

16GB: A[15:0]

32GB: A[16:0] (2)

64GB: A[17:0] (3)

BA[1:0], BG[1:0], A[17:0] -

32GB: A[15:0]

64GB: A[16:0] (2)

128GB: A[17:0] (3)

Clock CK0/CK0# CK0/CK0#, CK1/CK1# CK0/CK0# CK0/CK0#, CK1/CK1# CK0/CK0#, CK1/CK1# CK0/CK0#, CK1/CK1#
Command ODT, CS#, CKE, ACT#, RAS#/A16, CAS#/A15, WE#/A14 ODT[1:0], CS#[1:0], CKE[1:0], ACT#, RAS#/A16, CAS#/A15, WE#/A14 ODT, CS#, CKE, ACT#, RAS#/A16, CAS#/A15, WE#/A14 ODT[1:0], CS#[1:0], CKE, ACT#, RAS#/A16, CAS#/A15, WE#/A14 ODT, CS#[1:0], CKE, ACT#, RAS#/A16, CAS#/A15, WE#/A14 ODT, CS#[3:0], CKE, ACT#, RAS#/A16, CAS#/A15, WE#/A14
Parity PAR, ALERT# PAR, ALERT# PAR, ALERT# PAR, ALERT# PAR, ALERT# PAR, ALERT#
Other Pins SA[2:0], SDA, SCL, EVENT#, RESET# SA[2:0], SDA, SCL, EVENT#, RESET# SA[2:0], SDA, SCL, EVENT#, RESET# SA[2:0], SDA, SCL, EVENT#, RESET# SA[2:0], SDA, SCL, EVENT#, RESET# SA[2:0], SDA, SCL, EVENT#, RESET#

Notes to Table:

  1. DM/DBI pins are available only for DIMMs constructed using x8 or greater components.
  2. This density requires 4Gb x4 or 2Gb x8 DRAM components.
  3. This density requires 8Gb x4 DRAM components.
  4. This table assumes a single slot configuration. The Intel® Agilex™ memory controller can support up to 4 ranks per channel. A single slot interface may have up to 4 ranks, and a dual slot interface may have up to 2 ranks per slot. In either cse, the total number of ranks, calculated as the number of slots multiplied by the number of ranks per slot, must be less than or equal to 4.

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