External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 3/28/2022

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Document Table of Contents

5.1. Simulation Options

The following simulation options are available with the example testbench to improve simulation speed:
  • Skip calibration—Loads memory configuration settings and enters user mode, providing the fastest simulation time.

Simulation represents accurate controller efficiency and does not take into account board skew. This may cause a discrepancy in the simulated interface latency numbers. For more information regarding simulation assumptions and differences between RTL simulation and post-fit implementation, refer to the Simulation Versus Hardware Implementation chapter in the External Memory Interfaces Intel® Agilex™ FPGA EMIF IP Design Example User Guide.

Abstract I/O SSM

To improve simulation time, the Intel® Agilex™ EMIF IP for simulation implements an abstract I/O subsystem manager (Abstract I/O SSM). The Abstract I/O SSM is a behavioral implementation of the I/O SSM that executes the same calibration code while minimizing circuit complexity and processor delays. As a result of these optimizations, processor-generated events may occur at different times when compared with the true I/O SSM. The Abstract I/O SSM model is not currently supported in the Questa* simulator when two calibration IPs are instantiated. You can disable the Abstract I/O SSM by setting the iossm_use_model parameter to 0 in the simulation RTL or in your simulator; for the design example, the hierarchy for this parameter is: ed_sim.emif_cal.emif_cal.emif_cal.arch_inst.io_ssm.iossm_use_model .

Table 64.  Typical Simulation Times Using Intel® Agilex™ EMIF IP

Calibration Mode/Run Time (1)

Estimated Simulation Time

Small Interface (×8 Single Rank)

Large Interface (×72 Quad Rank)


  • Skip calibration
  • Preloads calculated settings

15 minutes

40 minutes

Note to Table:

  1. Uses one loop of driver test. One loop of driver is approximately 600 read or write requests, with burst length up to 64.
  2. Simulation times shown in this table are approximate measurements made using Synopsys VCS. Simulation times can vary considerably, depending on the IP configuration, the simulator used, and the computer or server used.
  3. In Intel® Quartus® Prime version 22.1 and later, skip calibration simulations may realize significant speed improvement when the Abstract I/O SSM model is used.