External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 3/28/2022
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11.9.8.5. Examples of Configuring the TG2 Traffic Generator

Example 1: Configuring TG2 to Write and Read from All Memory Locations with Alternating 0x555_5555_5555_5555 and 0xAAA_AAAA_AAAA_AAAA Data Pattern

In this example, 227 logical addresses are available on the EMIF controller. This example is a x72 DDR4 interface, configured to use Quarter Rate (QR) user logic.

Figure 215. Address Width for Memory IP

To write to all memory locations for a memory IP, starting from address=0x0 , it is necessary to satisfy the following requirement:

TG_LOOP_COUNT x TG_BURST_LENGTH x TG_WRITE_COUNT = Total Logical Address Available

For this example, assume the following:

  • TG_BURST_LENGTH = 64 (in decimal) or TG_BURST_LENGTH = 0x40 (in hexadecimal).
  • TG_WRITE_COUNT = 1.

You can calculate the required TG_LOOP_COUNT as follows:

TG_LOOP_COUNT = Total Logical Address Available / (TG_WRITE_COUNT x TG_BURST_LENGTH)
= 227/64
= 2097152 (in decimal)
= 0x20_0000 (in hexadecimal)

To configure the TG2 using core logic, follow these steps:

  1. Write to TG_CLEAR with data=0xF to clear all the failure status registers.
  2. Configure the registers with the value specified in table 1 below.
  3. Write to TG_START to start the TG2 using the configuration in step 2. This starts the traffic test in user mode.
  4. Read from TG_TEST_COMPLETE until the read data =0x1, indicating the traffic test has completed.
  5. Read from TG_PASS, TG_FAIL, and TG_TIMEOUT to check the test result.
    • TG_PASS. A value of 1 indicates that the traffic test passed at the end of all test stages.
    • TG_FAIL. A value of 1 indicates that the configured traffic finished running but a failure (read miscompare) was observed. You may read from other relevant registers to get more information about the failure. Refer to the Configuration and Status Registers table for information on the available registers.
    • TG_TIMEOUT. A value of 1 indicates that a read response was not received from the interface for one or more read commands.
Table 168.  TG2 Configuration to Write and Read from All Memory Locations in Example 1
Address Register Name Value Remarks
0x8 TG_LOOP_COUNT 0x20_0000 Require 2097152* 64 to cover all memory locations.
0xC TG_WRITE_COUNT 0x1  
0x10 TG_READ_COUNT 0x1  
0x14 TG_WRITE_REPEAT_COUNT 0x1  
0x18 TG_READ_REPEAT_COUNT 0x1  
0x1C TG_BURST_LENGTH 0x40 Require 2097152* 64 to cover all memory locations.
0x38 TG_RW_GEN_IDLE_COUNT 0x1  
0x3C TG_RW_GEN_LOOP_IDLE_COUNT 0x1  
0x40 TG_SEQ_START_ADDR_WR_L 0x0 Lower 32-bit of start write address.
0x44 TG_SEQ_START_ADDR_WR_H 0x0 Upper 32-bit of start write address.
0x48 TG_ADDR_MODE_WR 0x1 Sequential Addressing.
0x50 TG_RETURN_TO_START_ADDR 0x0  
0x74 TG_SEQ_ADDR_INCR 0x40 Must match the burst length in this example.
0x78 TG_SEQ_START_ADDR_RD_L 0x0 Lower 32-bit of start read address.
0x7C TG_SEQ_START_ADDR_RD_H 0x0 Upper 32-bit of start read address.
0x80 TG_ADDR_MODE_RD 0x1 Sequential Addressing. Must match the TG_ADDR_MODE_WR.
0xB4 TG_USER_WORM_EN 0x0 Disable WORM mode.
0xE80 TG_BYTEEN_SEL 0x0 Fixed Pattern.
0xC00 TG_PPPG_SEL 0x0 Fixed Pattern.
0x400 TG_DATA_SEED 0x5555_5555 For DG0 (DQ0/8/16/24/32/40/48/56/64).
0x404 TG_DATA_SEED 0xAAAA_AAAA For DG1 (DQ1/9/17/25/33/41/49/57/65).
0x408 TG_DATA_SEED 0x5555_5555 For DG2 (DQ2/10/18/26/34/42/50/58/66).
0x40C TG_DATA_SEED 0xAAAA_AAAA For DG3 (DQ3/11/19/27/35/43/51/59/67).
0x410 TG_DATA_SEED 0x5555_5555 For DG4 (DQ4/12/20/28/36/44/52/60/68).
0x414 TG_DATA_SEED 0xAAAA_AAAA For DG5 (DQ5/13/21/29/37/45/53/61/69).
0x418 TG_DATA_SEED 0x5555_5555 For DG6 (DQ6/14/22/20/38/46/54/62/70).
0x41C TG_DATA_SEED 0xAAAA_AAAA For DG7 (DQ7/15/23/31/39/47/55/63/71).
0x800 TG_BYTEEN_SEED 0xFFFF_FFFF For Byte 0.
0x804 TG_BYTEEN_SEED 0xFFFF_FFFF For Byte 1.
0x808 TG_BYTEEN_SEED 0xFFFF_FFFF For Byte 2.
0x80C TG_BYTEEN_SEED 0xFFFF_FFFF For Byte 3.
0x810 TG_BYTEEN_SEED 0xFFFF_FFFF For Byte 4.
0x814 TG_BYTEEN_SEED 0xFFFF_FFFF For Byte 5.
0x818 TG_BYTEEN_SEED 0xFFFF_FFFF For Byte 6.
0x81C TG_BYTEEN_SEED 0xFFFF_FFFF For Byte 7.
0x820 TG_BYTEEN_SEED 0xFFFF_FFFF For Byte 8.

Example 2: Configuring TG2 to Run with an Infinite Loop

  1. Clear all the failure status registers. Write to TG_CLEAR with data=0xF.
  2. Configure the TG2 with the access and data pattern you want.
  3. Write to TG_LOOP_COUNT with data=0x0.
  4. Write to TG_START with a 0 or 1 to start TG2.
  5. To stop the TG2 while running an infinite loop, write to TG_LOOP_COUNT with data=0x1.

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