External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 3/28/2022
Public

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11.8.1. Reading the Default Traffic Generator Status

To observe the overall traffic generator (TG) status, you should route each of the following top-level signals to external pins connected to LEDs or to test points for monitoring with an oscilloscope: traffic_gen_pass, traffic_gen_fail, and traffic_gen_timeout. Alternatively, you can enable In-System Sources and Probes (ISSPs) in the design, which you can read using Signal Tap, the System Console, or the Calibration Debug Toolkit.

The traffic generator provides detailed failure information, as described below.

Pass-Not-Fail (PNF) bits

The width of the pnf_per_bit bus equals the data width on the Avalon Control interface. Each PNF bit represents the status of each data bit, as gathered from comparison between the data written to a particular address and the read response from the same address.

pnf_per_bit[x] is high as long as no write-read mismatches have occurred on bit x. PNF bits are persistent, meaning that once a bit is set low due to a data mismatch, it remains low until the next TG reset.

The PNF bits map to the control interface data bits in a 1:1 manner. To understand the mapping to data pins on the memory side, consider the example of a 32-bit DDR4, quarter-rate interface. This interface has a control data width of 256, where the following are true:

  • pnf[0] maps to dq[0] for the first beat (immediately after the preamble) of a BL8 memory read operation
  • pnf[1] maps to dq[1] for the first beat (immediately after the preamble) of a BL8 memory read operation
  • ...
  • pnf[31] maps to dq[31] for the first beat (immediately after the preamble) of a BL8 memory read operation
  • pnf[32] maps to dq[0] for the second beat of a BL8 memory read operation
  • ...
  • pnf[64] maps to dq[0] for the third beat of a BL8 memory read operation
  • ...
  • pnf[96] maps to dq[0] for the fourth beat of a BL8 memory read operation
  • ...
  • pnf[128] maps to dq[0] for the fifth beat of a BL8 memory read operation
  • pnf[160] maps to dq[0] for the sixth beat of a BL8 memory read operation
  • ...
  • pnf[192] maps to dq[0] for the seventh beat of a BL8 memory read operation
  • ...
  • pnf[224] maps to dq[0] for the final beat (immediately before the postamble) of a BL8 memory read operation

A similar mapping approach applies to any other supported interface memory bus width.

Information about First Observed Failure

The traffic generator has registers that store the address of the first data mismatch, the expected data, the read data, etcetera. These registers can be read through ISSPs or by adding them to a Signal Tap waveform. For a detailed description of all ISSPs that are present in the example design, refer to ISSPs Tab.

Write-Once-Read-Many (WORM) Mode

When enabled, WORM mode causes the traffic generator to provide information about failures by performing an additional read from the address where the failure occurred. You can then read the TG status registers and analyze the results accordingly:

  • If both reads produced the same readdata value, then the error was likely in the write path.
  • If each read produced a different readdata value, then the error is likely in the read path.

To enable WORM mode, set the WORM ISSP HIGH. When the TG is reset while the WORM bit is set to HIGH, TG runs in WORM mode. Refer to ISSPs Tab for a list of ISSPs that are present in a design example. These ISSPs store the data observed while TG runs in this mode.

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