External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 3/28/2022

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9.5. Top-level Parameterization File

The top-level parameterization file contains all the necessary IP information to perform the three SPICE simulations to obtain the address and command, DQ-Write, and DQ-Read data eyes.

To enable your simulations, follow these steps:

  1. Modify the required parameters to supply file name locations for IBIS models and Touchstone models.
  2. Modify the IP-supplied parameters to correct any discrepancies between the generated simulation parameters and your design (optional).
  3. Import the contents of the IP-generated <instance_name>_altera_emif_arch_fm_<ip_version>_<uniquification_code>_ip_parameter.dat file into the membsi_ip_parameter.dat file.