External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 3/28/2022
Public

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7.4.3.3. Power Delivery Recommendation for QDR-IV Configurations

This topic describes power distribution network (PDN) design guidelines for QDR-IV configurations.
Note: For information on power distribution network design at the FPGA to meet timing margins, refer to the AG014 PDN design guideline.

The number of decoupling capacitors is based on a single channel. If multiple channels are sharing the same power rail, the number of decoupling capacitors at the memories must be scaled accordingly for all channels

Physically small decoupling capacitors are recommended to minimize area, inductance, and resistance on the PDN path on the printed circuit board.

The following are recommended guidelines for designing power delivery for QDR-IV memory:

  • Use 0.1uF in 0402 size to minimize inductance.
  • Make VTT voltage decoupling close to termination resistors.
  • Connect decoupling capacitors between VTT and ground at the memory device.
  • Use a 0.1uF capacitor for every other VTT pin and a 0.01uF cap for every VDD and VDDQ pin.

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